Happy New Year! Well, at least for those of you who celebrate the Lunar New Year (which was often called “Chinese New Year” back before I was old enough to drive). If you don’t normally celebrate now, then take the rest of the day off and tell your boss I told you to*.
So back in what seems like another lifetime, I said “The official PCI Express Base Specification Revision 4.0 final specification has been released – get it here: https://members.pcisig.com/wg/PCI-SIG/document/10912?downloadRevision=active
“What’s in a name? that which we call a rose by any other word would smell as sweet” How many times do you get Shakespeare in a tech blog? Well, here at ExpressYourself we like to cover all the bases 🙂 (I’m fond of announcing that “I have a poetic license and I’m not afraid to use it!” much to the chagrin of my children I’m sure.)
At the PCI-SIG DevCon in June 2017 two announcements were made with regards to PCI Express specifications. The first is that the specification for PCIe 4.0 is now at version 0.9. The second and even more interesting announcement was of the new PCI Express 5.0 specification at the initial 0.3 version. With the PCI Express 5.0 announcement, the industry gets another doubling of speed from 16.0GT/s to 32GT/s per lane providing a bandwidth for a x16 (16 lanes) at about 128GB/s. The chart below provides a comparison for the different generations of PCIe rates and bandwidth.
Synopsys has a long history of working with ecosystem partners as part of the development process, especially when new versions of a specification are rolled out. The PCIe 4.0 specification has taken a long time, but that hasn’t slowed us down. If you remember from previous postings, some of our PCIe 4.0 demos include:
Ok, so maybe that’s not the 6P’s (or 5P’s or 7P’s depending on where you first learned it) most folks may be familiar with, but it seemed pretty proper for a performance posting…plus someone said Solomon is a serious sucker for alliterations! (Hey, now that I can no longer make IDF jokes, you just KNEW I was going to have to find another outlet!)
…or in my case, I think it’s “Where have you been until the Ides of March????”
Ok, so the title reference might be a bit aged for many of our readers… You young-uns can check out this YouTube video for a hint. On the offhand chance that you missed the email from PCI-SIG, I’ll give a (PCI-SIG members-only of course) link directly in to the new 0.7 Draft of PCI Express 4.0: https://members.pcisig.com/wg/PCI-SIG/document/download/9977
Pop quiz! Which section of the PCI Express Base Specification covers bifurcation? Here, I’ll even wait while you look….
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.