Ah it’s been a long time coming, but as many of you know, last week’s PCI-SIG Compliance Workshop #110 was the first official testing for PCI Express 4.0 compliance testing. I’m super-excited to be able to say that Synopsys had *BOTH* Endpoint and Root Complex devices pass the testing with our 16GT/s PHY IP in several different silicon processes! (Ok, ok, you can probably already guess that some of those PHYs are capable of even higher speeds, but since we’re talking just about PCIe 4.0 compliance today I won’t go into that…) Within the next few weeks, you’ll finally be able to see “PCIe 4.0 Compliant” devices on the PCI-SIG Integrator’s List, and there will be a goodly number of Synopsys entries!
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Posted in PCI Express, PCI-SIG, Uncategorized
Richard has been talking about how long it’s been since he’s posted. I have to say, it’s been forever since I’ve posted a blog and I’ll need to work on that in 2019. Yes, I’m still alive and kicking and so much has happened since I’ve posted. More on that in another post.
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Posted in Architecture, PCI Express, PCI-SIG, Specification, Uncategorized
I’m afraid that I’m showing my age again with this title, and in truth time has shown that video did *NOT* kill off radio/audio-only media. In much the same way, I believe that nothing takes the place of an in-person presentation. Even when an audience is not asking questions, I find that there’s a connection between them and the speaker which is different for every occasion – even if the underlying material doesn’t change.
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Posted in PCI Express, PCI-SIG, Uncategorized
Whew, what a week! That’s another PCI-SIG Developers Conference in the books though.
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So back in what seems like another lifetime, I said
“The official PCI Express Base Specification Revision 4.0 final specification has been released – get it here: https://members.pcisig.com/wg/PCI-SIG/document/10912?downloadRevision=active
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…or in my case, I think it’s “Where have you been until the Ides of March????”
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Posted in PCI Express, Uncategorized
Sorry this is so last-minute, but any of you who are at Flash Memory Summit this week, please stop by Tuesday night for “Beer, Pizza and Chat with the Experts” (7pm-8:30pm) where I’ll have a table on SSD Interfaces. Of course this will be completely neutral 😀
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Hopefully all of you have made plans to attend this year’s PCI-SIG Developers Conference (aka Devcon) next week in Santa Clara. This is THE event to learn about PCI Express technology, and network with your fellow PCIe ecosystem members. Of course Synopsys will be there, both on the exhibition hall floor and in the Member Implementation tracks. Come listen to the big dogs from Synopsys R&D teach you (and our competitors) about two important topics. First, come by Track 3 on Tuesday at 3:30pm to hear how we got our DesignWare Root Port IP for PCI Express on the PCI-SIG Integrator’s List as the first *EVER* from an IP provider! Don’t miss the 10:30am Wednesday morning session (also in Track 3) on PCI Express in automotive applications. Yes, it’s true, I’m taking a bit of a rest on this one and “only” presenting PCI-SIG sessions this time, but the other Synopsys presenters will keep you informed, even if they’re not as funny as I think I am 😀
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Posted in Architecture, PCI Express, PCI-SIG, Uncategorized
“What’s this?!?!? A blog posting from Richard? Wasn’t he killed in a fiery camel-riding crash at the last PCI-SIG Israel event or something?”
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Posted in PCI Express, PCI-SIG, Specification, Uncategorized
Scott Knowlton
Richard Solomon