Wow, the last weeks have been just crazy crazy! Luckily Scott’s been on top of the blog for the last month or so, or you might have thought we’d dropped off the face of the earth. Actually, May was very hectic for me – I don’t think I had more than 36 hours straight at home for the last few weeks of the month. Scott and I visited some customers out in Texas, then there was the semi-annual Synopsys FAE training, and finally (lo-and-behold) I took an actual vacation! Squeezing in a week in Europe between FAE training and Devcon seemed like a good idea when I scheduled it, but Murphy’s Law came into play on my return. My 12-hour layover at home turned into arriving the next morning, changing suitcases and catching a late afternoon flight 4hrs after I arrived! All for you dear readers, all so I could make it to the Developers Conference.
For those of you coming to the PCI-SIG DevCon, you should stop by and visit the Synopsys booth (Booth 8 ) to learn about our high-quality, silicon-proven DesignWare IP portfolio for PCI Express, which includes controllers, PHYs and verification IP. See how our robust IP development methodology, extensive investment in quality, IP prototyping, software development, and comprehensive technical support enables designers to accelerate time-to-market and reduce integration risk.
This seems strange to ask you, but “are you ready to start designing with PCI Express 4.0?” Why does it seem strange to ask? It’s because PCI Express 4.0 was announced in November 2011 and the 0.3 version of the specification isn’t out yet (although I hear that it could happen in a few days). My very first blog posting was about PCI Express 4.0 on November 4th, 2012 “World Domination: PCI Express (4), Dr. Evil (0)”. With so much time passing, why would I write about it today and ask if you’re ready to start designing with PCI Express 4.0? Here is why: Synopsys announced our PCI Express 4.0 solution today. You can read all about it via our press release “Synopsys Unveils Industry’s First Complete PCI Express 4.0 solution”. We are providing digital controllers, PHYs and Verification IP that all support the new 16GT/s speeds in the PCI Express 4.0 specification, so you can include PCI Express 4.0 into your latest designs. Here are the highlights from the press release:
Sorry, I’ve been very delinquent in posting – it’s been a busy month! As you might guess from the title, one of the things keeping me busy was doing last year’s income taxes. (Non-USA folks might not know the dread with which Americans approach April 15th each year – the day our income taxes are due.) Changing employers of course complicated things a little (apparently I managed to overpay Social Security) and I was lucky enough to have some nice gains in the stock market. Unfortunately I had some nice gains in the stock market so I went from filling out the “send us most of your money” tax forms to the “send us all your money” tax forms. A time-honored American tradition is finding legal ways to manipulate money so as to pay less in taxes – apparently I’m not very good at this!
Well, I should know better, but in my New Year’s Resolution post I said “Those of you who are PCI-SIG members should soon see what PCI-SIG calls the ‘0.3 draft’ of PCIe 4.0…” Sigh. Did I say “soon”? I meant, “eventually” – oh crud, no, let’s be honest, I meant “soon”. If truth be told, I really thought “soon” would be before the end of Q1 … yeah, I know, that’s today…thus this blog posting.
Unless you are Rob Ford of course, if you live in North America, you probably spent your Sunday morning much like I did – going around to every clock in the house and setting it an hour forward. If not, or if you ARE Rob Ford, then I’m sorry I didn’t post this blog entry on Saturday…
So long 2013, you were a great year for PCI Express (and for me personally) but your 365 days of fame are winding down as I write this. You gave us lots of new PCI Express features – especially around low-power. First you brought the L1 Substates ECN providing “traditional” PCIe PHYs with impressive power savings modes, and later on the M-PCIe ECN opening up the PCI Express infrastructure to MIPI M-PHYs in what Scott aptly described as A Match Made in Heaven. Later you even had the much anticipated M.2 Specification to define a wide variety of PCIe mobile-oriented plug-in cards which enable some exciting new PC/Tablet form-factors.
Yes, I said “burgers” and not “burghers” but more on that in a bit… I have to apologize for the lateness of this posting, I didn’t realize until I was writing the last one that I had NOT actually typed this up. So here I’ve been wondering why no burger/burgher cracks have been showing up in my inbox and it turns out that the main reason is this blog post has only been in my head until now. Sigh.
No, no, I didn’t say “Off to the IDF” – I mean the Intel Developer Forum:
Oh darn, I almost forgot! If you’ve enjoyed my live shows, I mean presentations, mark your calendars for Tuesday August 27th at 9am Pacific and head on over to http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=synopsys_aug2713 along with two or three hundred of your closest friends and sign up for my first ever attempt at a webinar.