Ah it’s been a long time coming, but as many of you know, last week’s PCI-SIG Compliance Workshop #110 was the first official testing for PCI Express 4.0 compliance testing. I’m super-excited to be able to say that Synopsys had *BOTH* Endpoint and Root Complex devices pass the testing with our 16GT/s PHY IP in several different silicon processes! (Ok, ok, you can probably already guess that some of those PHYs are capable of even higher speeds, but since we’re talking just about PCIe 4.0 compliance today I won’t go into that…) Within the next few weeks, you’ll finally be able to see “PCIe 4.0 Compliant” devices on the PCI-SIG Integrator’s List, and there will be a goodly number of Synopsys entries!
“…by the dawn’s early light..”
Richard has been talking about how long it’s been since he’s posted. I have to say, it’s been forever since I’ve posted a blog and I’ll need to work on that in 2019. Yes, I’m still alive and kicking and so much has happened since I’ve posted. More on that in another post.
No, no, “it” does NOT refer to “get Richard back on the blog after some 4 months of silence” – although I think Scott was starting to think that and was probably considering threats of bodily harm!
I’m afraid that I’m showing my age again with this title, and in truth time has shown that video did *NOT* kill off radio/audio-only media. In much the same way, I believe that nothing takes the place of an in-person presentation. Even when an audience is not asking questions, I find that there’s a connection between them and the speaker which is different for every occasion – even if the underlying material doesn’t change.
You’re probably thinking “Wait a minute Richard, it’s not May anymore!” which is why I titled this “May 32nd…”
PCI-SIG Board Election Time that is – please vote before Tuesday at noon Pacific!
Well things are about to get busier – though given I got off a plane Thursday night from the PCI-SIG Compliance Workshop #105 and got on another one less than 12 hours later to go to a family wedding… Perhaps my definition of “busy” is a bit suspect!
At the PCI-SIG DevCon in June 2017 two announcements were made with regards to PCI Express specifications. The first is that the specification for PCIe 4.0 is now at version 0.9. The second and even more interesting announcement was of the new PCI Express 5.0 specification at the initial 0.3 version. With the PCI Express 5.0 announcement, the industry gets another doubling of speed from 16.0GT/s to 32GT/s per lane providing a bandwidth for a x16 (16 lanes) at about 128GB/s. The chart below provides a comparison for the different generations of PCIe rates and bandwidth.
Synopsys has a long history of working with ecosystem partners as part of the development process, especially when new versions of a specification are rolled out. The PCIe 4.0 specification has taken a long time, but that hasn’t slowed us down. If you remember from previous postings, some of our PCIe 4.0 demos include: