Express Yourself

Archive for the 'PCI-SIG' Category

 

OCP Can You See…

“…by the dawn’s early light..”

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Posted in PCI Express, PCI-SIG, Uncategorized |

 

First PCIe 5.0 32GT/s PHY IP

Richard has been talking about how long it’s been since he’s posted. I have to say, it’s been forever since I’ve posted a blog and I’ll need to work on that in 2019. Yes, I’m still alive and kicking and so much has happened since I’ve posted. More on that in another post.

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Posted in Architecture, PCI Express, PCI-SIG, Specification, Uncategorized |

 

They Said It Couldn’t Be Done! (PCIe 5.0)

No, no, “it” does NOT refer to “get Richard back on the blog after some 4 months of silence” – although I think Scott was starting to think that and was probably considering threats of bodily harm!

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Posted in PCI Express, PCI-SIG |

 

Video Killed the Radio Star?

I’m afraid that I’m showing my age again with this title, and in truth time has shown that video did *NOT* kill off radio/audio-only media.  In much the same way, I believe that nothing takes the place of an in-person presentation.  Even when an audience is not asking questions, I find that there’s a connection between them and the speaker which is different for every occasion – even if the underlying material doesn’t change.

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Posted in PCI Express, PCI-SIG, Uncategorized |

 

May (32nd) Musings on Munich…

You’re probably thinking “Wait a minute Richard, it’s not May anymore!” which is why I titled this “May 32nd…”

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Posted in Architecture, Automotive, Market Adoption, PCI Express, PCI-SIG |

 

It’s That Time of Year… Election Time

PCI-SIG Board Election Time that is – please vote before Tuesday at noon Pacific!

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Posted in PCI Express, PCI-SIG |

 

Summer of DevCons…

Well things are about to get busier – though given I got off a plane Thursday night from the PCI-SIG Compliance Workshop #105 and got on another one less than 12 hours later to go to a family wedding…  Perhaps my definition of “busy” is a bit suspect!

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Posted in PCI Express, PCI-SIG |

 

1, 2, 3, 4, 5… It’s Official, PCIe 5.0 is Announced

At the PCI-SIG DevCon in June 2017 two announcements were made with regards to PCI Express specifications. The first is that the specification for PCIe 4.0 is now at version 0.9. The second and even more interesting announcement was of the new PCI Express 5.0 specification at the initial 0.3 version. With the PCI Express 5.0 announcement, the industry gets another doubling of speed from 16.0GT/s to 32GT/s per lane providing a bandwidth for a x16 (16 lanes) at about 128GB/s. The chart below provides a comparison for the different generations of PCIe rates and bandwidth.

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Posted in Architecture, General Protocol, Market Adoption, PCI Express, PCI-SIG, Specification |

 

PCIe 4.0 Ecosystem with Synopsys and Mellanox

Synopsys has a long history of working with ecosystem partners as part of the development process, especially when new versions of a specification are rolled out. The PCIe 4.0 specification has taken a long time, but that hasn’t slowed us down. If you remember from previous postings, some of our PCIe 4.0 demos include:

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Posted in General Protocol, Market Adoption, PCI Express, PCI-SIG, PHY, Specification |

 

The New Spec Draft’s Here, The New Spec Draft’s Here!

Ok, so the title reference might be a bit aged for many of our readers… You young-uns can check out this YouTube video for a hint.  On the offhand chance that you missed the email from PCI-SIG, I’ll give a (PCI-SIG members-only of course) link directly in to the new 0.7 Draft of PCI Express 4.0: https://members.pcisig.com/wg/PCI-SIG/document/download/9977

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Posted in PCI Express, PCI-SIG, Specification |