…at least for Richard 🙂
Posted in PCI Express
“What’s in a name? that which we call a rose by any other word would smell as sweet” How many times do you get Shakespeare in a tech blog? Well, here at ExpressYourself we like to cover all the bases 🙂 (I’m fond of announcing that “I have a poetic license and I’m not afraid to use it!” much to the chagrin of my children I’m sure.)
Posted in PCI Express
At the PCI-SIG DevCon in June 2017 two announcements were made with regards to PCI Express specifications. The first is that the specification for PCIe 4.0 is now at version 0.9. The second and even more interesting announcement was of the new PCI Express 5.0 specification at the initial 0.3 version. With the PCI Express 5.0 announcement, the industry gets another doubling of speed from 16.0GT/s to 32GT/s per lane providing a bandwidth for a x16 (16 lanes) at about 128GB/s. The chart below provides a comparison for the different generations of PCIe rates and bandwidth.
Synopsys has a long history of working with ecosystem partners as part of the development process, especially when new versions of a specification are rolled out. The PCIe 4.0 specification has taken a long time, but that hasn’t slowed us down. If you remember from previous postings, some of our PCIe 4.0 demos include:
Ok, so maybe that’s not the 6P’s (or 5P’s or 7P’s depending on where you first learned it) most folks may be familiar with, but it seemed pretty proper for a performance posting…plus someone said Solomon is a serious sucker for alliterations! (Hey, now that I can no longer make IDF jokes, you just KNEW I was going to have to find another outlet!)
Posted in PCI Express
…or in my case, I think it’s “Where have you been until the Ides of March????”
Ok, so the title reference might be a bit aged for many of our readers… You young-uns can check out this YouTube video for a hint. On the offhand chance that you missed the email from PCI-SIG, I’ll give a (PCI-SIG members-only of course) link directly in to the new 0.7 Draft of PCI Express 4.0: https://members.pcisig.com/wg/PCI-SIG/document/download/9977
Pop quiz! Which section of the PCI Express Base Specification covers bifurcation? Here, I’ll even wait while you look….
Scott and I are out at IDF (Intel Developer Forum – not the Tavor-wielding IDF) this week, where the keynote yesterday was all about Virtual Reality, Augmented Reality, and Merged Reality …. oddly not much was said about plain old real reality. If you missed us last week at Flash Memory Summit (FMS) please stop by Booth #230 and say “Hi”. Heck, even if you didn’t miss us, come by anyway! Speaking of FMS, I should first give you an…. FMS AAR (After Action Report) I apologize for not posting sooner, but after spending so much time last week chanting under my breath my favorite old Polish folk-saying (“Not my circus, not my monkeys!”) I was struggling with exactly what to post about FMS. Suffice it to say that there were a number of logistical “challenges” with the show itself – culminating in a no-show of the moderator for the PCIe/NVMe session. However, I did have a good turnout of 50-60 folks for my session on using PCIe 4.0 in SSDs. I really appreciated everyone’s patience as the speakers worked out our own lineup and introductions (and no, for the record, despite how I introduced him, Debendra didn’t *actually* invent a banana peeler). There was definitely a lot of interest in PCIe 4.0 from SSD folks and that was evident in our booth traffic as well. This shouldn’t be surprising to anyone given new technologies in non-volatile media and the relative ease of aggregating NAND (or other) chips to get extremely high bandwidth, not to mention that most common PCIe SSD form-factors are limited to 4 lanes. (Remember that SFF-8639, now sometimes called U.2, and the newish M.2 form-factor both top out at PCIe x4 configurations so their only real choice for more bandwidth is higher signaling speed.) Regardless of the hiccups, thanks for all those who stopped by – including some old friends and colleagues:
Hopefully all of you have made plans to attend this year’s PCI-SIG Developers Conference (aka Devcon) next week in Santa Clara. This is THE event to learn about PCI Express technology, and network with your fellow PCIe ecosystem members. Of course Synopsys will be there, both on the exhibition hall floor and in the Member Implementation tracks. Come listen to the big dogs from Synopsys R&D teach you (and our competitors) about two important topics. First, come by Track 3 on Tuesday at 3:30pm to hear how we got our DesignWare Root Port IP for PCI Express on the PCI-SIG Integrator’s List as the first *EVER* from an IP provider! Don’t miss the 10:30am Wednesday morning session (also in Track 3) on PCI Express in automotive applications. Yes, it’s true, I’m taking a bit of a rest on this one and “only” presenting PCI-SIG sessions this time, but the other Synopsys presenters will keep you informed, even if they’re not as funny as I think I am 😀
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.