At the PCI-SIG DevCon in June 2017 two announcements were made with regards to PCI Express specifications. The first is that the specification for PCIe 4.0 is now at version 0.9. The second and even more interesting announcement was of the new PCI Express 5.0 specification at the initial 0.3 version. With the PCI Express 5.0 announcement, the industry gets another doubling of speed from 16.0GT/s to 32GT/s per lane providing a bandwidth for a x16 (16 lanes) at about 128GB/s. The chart below provides a comparison for the different generations of PCIe rates and bandwidth.
The PCI-SIG Compliance workshop #84 is taking place December 4-7 in Milpitas, California. At the workshop, you can test your PCIe 3.0 device as part of the “official FYI testing” to see if your product passes compliance. However, “FYI” testing is “For Your Information” and not “official testing”, so even if your product passes compliance you won’t be able to list it on the PCIe 3.0 Integrator’s list because this is only FYI testing. Based on the ramp for Gen1 and Gen2, I’d expect “official testing” for Gen 3 to begin by mid next year.