I’ve just spent the last couple of days at PCI-SIG’s DevCon and all I can say is WOW! I’ve been working with PCIe since 2003 and have been to every PCI-SIG Developer’s Conference since then. I don’t recall there ever being one with such a high level of excitement and large attendance as this one. I’m sure this DevCon had record attendance.
While PCI Express has been the dominant interconnect for chips that target personal computing, digital home, server, storage and networking applications, it has yet to be popular in products for the mobile market. Battery based devices like tablets and smartphones have ultra-low power requirements, placing a completely different emphasis on PCI Express. Great strides have been made to reduce power in the PCI Express protocol, with enhancements like half-swing drivers, Dynamic Power Allocation (DPA) controls, Latency Tolerance Reporting (LTR), Optimized Buffer Flush/Fill (OBFF) and the relatively new power-saving L1 Substates. However, the challenges of driving PCI Express’ high data rates across 16” to 20” server channels have kept the power requirements of the PCI Express PHYs well above what mobile devices can tolerate. If PCI Express was ever going to extend into the world of ultra-low power mobile devices, something drastic would have to be done.
Synopsys is hosting our annual user’s group meeting (SNUG) at the Santa Clara convention center this week. Within SNUG we feature an IP Summit which includes presentations and tutorials on many of the IPs that Synopsys offers. In this year’s SNUG, we have eight in-depth technical sessions on PCI Express, 10G SerDes, FinFETs, DDR4, embedded memories and standard logic libraries and more. If you haven’t already registered, you can register on-site and it’s free! To see what’s happening at the IP Summit, you can use the IP Summit at-a-glance here: http://www.synopsys.com/IP/Pages/ipsummit2013.aspx
For over nine years, our customers have successfully implemented Synopsys’ DesignWare® PCI Express IP into their SoCs. We just announced the new DesignWare Enterprise 10G PHY. The 28-nm PHY is multilingual, speaking PCI Express 3.0, 10GBASE-KR, 10GBASE-KX4, 1000BASE-KX, CEI-6G-SR, SGMII and QSGMII and supports data rates from 1.25Gbps to 10.3Gbps per lane. With support for the IEEE Energy Efficient Ethernet (EEE) standard, the PHY’s low power consumption targets a wide range of green, high-end networking and computing applications
Why 4? PCI-SIG announced last November the fourth generation of the PCI Express specification operating at 16GT/s providing twice the throughput of PCI Express (PCIe) 3.0. This is the fourth generation of a standard that has replaced PCI, PCI-X and AGP to become the de-facto interconnect in digital office, servers, networking, digital home, storage and is quickly improving its position in mobile as well. BTW: What’s a MIPI?