Now that my kids are back to school, things are calming down slightly. Well, ok, the chaos is shifting gears 🙂 I’m still recovering from IDF last week, and I owe you all a blog post about that, but I’ve been remiss in advising you of how you too can get “back to school” … with an upcoming Webinar on challenges you’ll face in PCI Express 4.0 design.
For those of you that didn’t get to see our demos at PCI-SIG DevCon, you can view these new summer blockbusters featuring the latest videos with your favorite Synopsys PCI Express Controller and PHY IP. These videos are rated two thumbs up by Scott and Richard!
As I put the final touches on preparations for the PCI-SIG Developer’s Conference and getting ready to show you multiple demos for our recently announced support for PCI Express 4.0 there are exciting developments happening from Synopsys that will make your next SoC design easier. Let’s face it. Your goal is to build a product and there are multiple steps that have to be completed before the product is done while doing this under increasingly shorter time to market goals. This means that we are trying to do as many tasks as possible in parallel and they need to stay coordinated. Today, Synopsys announced our new IP Accelerated Initiative that focuses on enabling designers to incorporate IP into your SoC design flow at multiple levels of the design process by using a coordinated solution between IP prototyping kits, software development kits and customized IP subsystems.
This seems strange to ask you, but “are you ready to start designing with PCI Express 4.0?” Why does it seem strange to ask? It’s because PCI Express 4.0 was announced in November 2011 and the 0.3 version of the specification isn’t out yet (although I hear that it could happen in a few days). My very first blog posting was about PCI Express 4.0 on November 4th, 2012 “World Domination: PCI Express (4), Dr. Evil (0)”. With so much time passing, why would I write about it today and ask if you’re ready to start designing with PCI Express 4.0? Here is why: Synopsys announced our PCI Express 4.0 solution today. You can read all about it via our press release “Synopsys Unveils Industry’s First Complete PCI Express 4.0 solution”. We are providing digital controllers, PHYs and Verification IP that all support the new 16GT/s speeds in the PCI Express 4.0 specification, so you can include PCI Express 4.0 into your latest designs. Here are the highlights from the press release:
Unless you are Rob Ford of course, if you live in North America, you probably spent your Sunday morning much like I did – going around to every clock in the house and setting it an hour forward. If not, or if you ARE Rob Ford, then I’m sorry I didn’t post this blog entry on Saturday…
Doesn’t that sound like the end of a commercial to buy something? SPAM? It’s not. This isn’t a plug to buy something. I promise.
What’s that? Yes, actually I *am* aware that New Year’s day was two weeks ago! What do you mean I’m late? No, no, wait I see the problem – not THAT kind of resolution (who keeps those anyway?), but the “number of pixels I can see” kind of resolution 🙂
So long 2013, you were a great year for PCI Express (and for me personally) but your 365 days of fame are winding down as I write this. You gave us lots of new PCI Express features – especially around low-power. First you brought the L1 Substates ECN providing “traditional” PCIe PHYs with impressive power savings modes, and later on the M-PCIe ECN opening up the PCI Express infrastructure to MIPI M-PHYs in what Scott aptly described as A Match Made in Heaven. Later you even had the much anticipated M.2 Specification to define a wide variety of PCIe mobile-oriented plug-in cards which enable some exciting new PC/Tablet form-factors.
I guess Heraclitus’ real quote is more like “Nothing endures but change” but I’m going to claim poetic license here and stick with “The only constant is change” – because I like the apparent contradiction better. Two events this week drove home the aptness of this quote to me. First we had the announcement that my previous employer LSI was being purchased by Avago. I’m not much of a business person, so I’m not sure quite how to interpret “drive LSI’s operating margins toward Avago’s current levels” but I do know how to interpret a stock price jump from around $8/share to around $11/share! (I believe the technical expression there is “Woo hoo!”) Second, we have a raft of internet news sources reporting that Calxeda is restructuring (or shutting down, depending on whose account you read). I don’t read “restructuring” (as Calxeda is quoted) quite the same as “shutting down”, but hey, we already established that I’m not a business guy. I guess I can’t complain too much about that use of poetic license though since I just exercised it at the top of this posting.
Way back in the day, Arsenio Hall did a number of comedy routines called “Things that make you go hmmm…” in which he pointed out any number of humorous examples of seemingly obvious examples of bad ideas, poorly named products, etc. In engineering circles we sometimes classify these as ideas which fail the obviousness test – as in “It should be obvious to the most casual observer that this is a bad idea”…