Richard has been talking about how long it’s been since he’s posted. I have to say, it’s been forever since I’ve posted a blog and I’ll need to work on that in 2019. Yes, I’m still alive and kicking and so much has happened since I’ve posted. More on that in another post.
You’re probably thinking “Wait a minute Richard, it’s not May anymore!” which is why I titled this “May 32nd…”
At the PCI-SIG DevCon in June 2017 two announcements were made with regards to PCI Express specifications. The first is that the specification for PCIe 4.0 is now at version 0.9. The second and even more interesting announcement was of the new PCI Express 5.0 specification at the initial 0.3 version. With the PCI Express 5.0 announcement, the industry gets another doubling of speed from 16.0GT/s to 32GT/s per lane providing a bandwidth for a x16 (16 lanes) at about 128GB/s. The chart below provides a comparison for the different generations of PCIe rates and bandwidth.
Pop quiz! Which section of the PCI Express Base Specification covers bifurcation? Here, I’ll even wait while you look….
Scott and I are out at IDF (Intel Developer Forum – not the Tavor-wielding IDF) this week, where the keynote yesterday was all about Virtual Reality, Augmented Reality, and Merged Reality …. oddly not much was said about plain old real reality. If you missed us last week at Flash Memory Summit (FMS) please stop by Booth #230 and say “Hi”. Heck, even if you didn’t miss us, come by anyway! Speaking of FMS, I should first give you an…. FMS AAR (After Action Report) I apologize for not posting sooner, but after spending so much time last week chanting under my breath my favorite old Polish folk-saying (“Not my circus, not my monkeys!”) I was struggling with exactly what to post about FMS. Suffice it to say that there were a number of logistical “challenges” with the show itself – culminating in a no-show of the moderator for the PCIe/NVMe session. However, I did have a good turnout of 50-60 folks for my session on using PCIe 4.0 in SSDs. I really appreciated everyone’s patience as the speakers worked out our own lineup and introductions (and no, for the record, despite how I introduced him, Debendra didn’t *actually* invent a banana peeler). There was definitely a lot of interest in PCIe 4.0 from SSD folks and that was evident in our booth traffic as well. This shouldn’t be surprising to anyone given new technologies in non-volatile media and the relative ease of aggregating NAND (or other) chips to get extremely high bandwidth, not to mention that most common PCIe SSD form-factors are limited to 4 lanes. (Remember that SFF-8639, now sometimes called U.2, and the newish M.2 form-factor both top out at PCIe x4 configurations so their only real choice for more bandwidth is higher signaling speed.) Regardless of the hiccups, thanks for all those who stopped by – including some old friends and colleagues:
Hopefully all of you have made plans to attend this year’s PCI-SIG Developers Conference (aka Devcon) next week in Santa Clara. This is THE event to learn about PCI Express technology, and network with your fellow PCIe ecosystem members. Of course Synopsys will be there, both on the exhibition hall floor and in the Member Implementation tracks. Come listen to the big dogs from Synopsys R&D teach you (and our competitors) about two important topics. First, come by Track 3 on Tuesday at 3:30pm to hear how we got our DesignWare Root Port IP for PCI Express on the PCI-SIG Integrator’s List as the first *EVER* from an IP provider! Don’t miss the 10:30am Wednesday morning session (also in Track 3) on PCI Express in automotive applications. Yes, it’s true, I’m taking a bit of a rest on this one and “only” presenting PCI-SIG sessions this time, but the other Synopsys presenters will keep you informed, even if they’re not as funny as I think I am 😀
The video at ARM TechCon of our 2nd PCIe Gen4 system got kind of lost in our end of the year, Thanksgiving, Christmas, New Years, End of the 1st Quarter rush. I know that my videos of PCIe won’t win any Oscars, but one wonders if someone is just hiding this masterpiece from the public eye. Ok, ok, it’s not a masterpiece, but I’m sure folks would like to see PCIe 4.0 in action. Just for fun, see if you can find my mistakes! There are at least 5!
There will be many demos at PCI-SIG 2015 this week declaring readiness for PCIe 4.0. Synopsys is one of them and will be showing PCIe 4.0 controllers, PHYs and verification IP. Of course, it’s great that the industry ecosystem is gearing up to support PCIe 4.0, but the specification is still under development and we have a way to go before PCIe 4.0 is finalized.
First, I’m sure there are some of you that look at this and think “what the heck”? PCIe being used in phones and tablet devices? How can that be? Rest assured PCIe has been used in mobile devices for a long time. Of course, laptops have been using it, but it’s also being used in phones and tablets for some time now. You may remember that PCIe with the MIPI M-PHY and say, that’s what Scott’s talking about, but no. This is the full blown PCI Express in these devices operating at 5.0GT/s and 8GT/s.
Well, we’re back from the PCI-SIG Developers Conference Israel 2015 and by now, between Scott and me we might make up one coherent person! (I know, given the blog frequency lately, you probably thought Scott and I had been kidnapped by aliens. I have no comment on that beyond “We’re back!“) This was the third Israel DevCon and as always I was pleased with the fantastic turnout. I mean, it’s a hardship going to Israel, but somehow we tough it out…