Richard has been talking about how long it’s been since he’s posted. I have to say, it’s been forever since I’ve posted a blog and I’ll need to work on that in 2019. Yes, I’m still alive and kicking and so much has happened since I’ve posted. More on that in another post.
Posts by Scott Knowlton, Director, Strategy & Solutions, Synopsys Solutions Group:
At the PCI-SIG DevCon in June 2017 two announcements were made with regards to PCI Express specifications. The first is that the specification for PCIe 4.0 is now at version 0.9. The second and even more interesting announcement was of the new PCI Express 5.0 specification at the initial 0.3 version. With the PCI Express 5.0 announcement, the industry gets another doubling of speed from 16.0GT/s to 32GT/s per lane providing a bandwidth for a x16 (16 lanes) at about 128GB/s. The chart below provides a comparison for the different generations of PCIe rates and bandwidth.
Synopsys has a long history of working with ecosystem partners as part of the development process, especially when new versions of a specification are rolled out. The PCIe 4.0 specification has taken a long time, but that hasn’t slowed us down. If you remember from previous postings, some of our PCIe 4.0 demos include:
The video at ARM TechCon of our 2nd PCIe Gen4 system got kind of lost in our end of the year, Thanksgiving, Christmas, New Years, End of the 1st Quarter rush. I know that my videos of PCIe won’t win any Oscars, but one wonders if someone is just hiding this masterpiece from the public eye. Ok, ok, it’s not a masterpiece, but I’m sure folks would like to see PCIe 4.0 in action. Just for fun, see if you can find my mistakes! There are at least 5!
There will be many demos at PCI-SIG 2015 this week declaring readiness for PCIe 4.0. Synopsys is one of them and will be showing PCIe 4.0 controllers, PHYs and verification IP. Of course, it’s great that the industry ecosystem is gearing up to support PCIe 4.0, but the specification is still under development and we have a way to go before PCIe 4.0 is finalized.
Richard and I will be at PCI-SIG. For any of you that go to PCI-SIG, you know Richard will be doing several presentations, some for PCI-SIG and some for Synopsys, so you can find him walking around. For me, you’ll be able to find me in the sessions or at the Synopsys booth during the exhibit times. Catch us or stop by the booth and tell us about your latest PCIe projects. Both of us love to hear about the latest ways you’re using PCI Express in your designs. We also like it when you tell us you read the blog.
First, I’m sure there are some of you that look at this and think “what the heck”? PCIe being used in phones and tablet devices? How can that be? Rest assured PCIe has been used in mobile devices for a long time. Of course, laptops have been using it, but it’s also being used in phones and tablets for some time now. You may remember that PCIe with the MIPI M-PHY and say, that’s what Scott’s talking about, but no. This is the full blown PCI Express in these devices operating at 5.0GT/s and 8GT/s.
For those of you that didn’t get to see our demos at PCI-SIG DevCon, you can view these new summer blockbusters featuring the latest videos with your favorite Synopsys PCI Express Controller and PHY IP. These videos are rated two thumbs up by Scott and Richard!
For those of you coming to the PCI-SIG DevCon, you should stop by and visit the Synopsys booth (Booth 8 ) to learn about our high-quality, silicon-proven DesignWare IP portfolio for PCI Express, which includes controllers, PHYs and verification IP. See how our robust IP development methodology, extensive investment in quality, IP prototyping, software development, and comprehensive technical support enables designers to accelerate time-to-market and reduce integration risk.
As I put the final touches on preparations for the PCI-SIG Developer’s Conference and getting ready to show you multiple demos for our recently announced support for PCI Express 4.0 there are exciting developments happening from Synopsys that will make your next SoC design easier. Let’s face it. Your goal is to build a product and there are multiple steps that have to be completed before the product is done while doing this under increasingly shorter time to market goals. This means that we are trying to do as many tasks as possible in parallel and they need to stay coordinated. Today, Synopsys announced our new IP Accelerated Initiative that focuses on enabling designers to incorporate IP into your SoC design flow at multiple levels of the design process by using a coordinated solution between IP prototyping kits, software development kits and customized IP subsystems.