Posted by Richard Solomon on August 20, 2019
Ah it’s been a long time coming, but as many of you know, last week’s PCI-SIG Compliance Workshop #110 was the first official testing for PCI Express 4.0 compliance testing. I’m super-excited to be able to say that Synopsys had *BOTH* Endpoint and Root Complex devices pass the testing with our 16GT/s PHY IP in several different silicon processes! (Ok, ok, you can probably already guess that some of those PHYs are capable of even higher speeds, but since we’re talking just about PCIe 4.0 compliance today I won’t go into that…) Within the next few weeks, you’ll finally be able to see “PCIe 4.0 Compliant” devices on the PCI-SIG Integrator’s List, and there will be a goodly number of Synopsys entries!
It’s been a long road getting the PCI-SIG 4.0 compliance program running, and there’s been a LOT of hard work put in by Synopsys engineers behind the scenes. I’ve mentioned before how the Synopsys PCIe 4.0 Root Complex was used to develop the lane margining tool, and we’ve had both that and our PCIe 4.0 Endpoint at *EVERY* FYI and pre-FYI compliance event the PCI-SIG has held. Obviously that benefits our customers, but I’m quite proud of how much Synopsys has stepped up from an industry perspective too. Even when we didn’t have anything new to test, management didn’t hesitate to put equipment and people on the road for yet another week of compliance testing, over and over again over the last couple of years. That was a BIG help for the development of the compliance program, and several times our engineers made special trips out to visit various companies doing test program development to help debug the tests themselves.
As an example of that commitment, here’s a Synopsys group photo taken at the Compliance Workshop – a huge shout out to Torrey and all the other folks who worked diligently to make this a reality.
I know the blog has been really quiet lately, and I want to emphasize how much of the compliance development work was being done by so many additional people, but hopefully with this behind us, I can finally catch up a bit on the blogging! (Was that a “The dog ate my homework!” excuse in disguise?)
Several folks at the PCI-SIG US Developers conference told me they missed the blog and the day-by-day blogging I did sometimes in the past. I’ll try and do more of that as we come up on the international Devcons, so do stay tuned! As an aside, if you missed my sessions at Devcon, you can find videos of them online (PCI-SIG members only, sorry): PCI-SIG Architecture Overview for a bit of the history and concepts underlying PCI Express, PCI Express Basics for those just starting out with PCI Express, and a new one I just did this year PCIe Architectures for Chip-to-Chip Interconnects which is about creative and interesting ways to use PCI Express that you might not have thought of.
If you’re not a PCI-SIG member or were just going bananas that you missed seeing me in person (yes, yes I said that with a straight face) then check out the PCI-SIG YouTube Channel and see me talk about PCI Express in Automotive.
P.S. If you’re not already subscribed to ExpressYourself then either click here for RSS or here for email so you don’t miss out on upcoming editions. Don’t hesitate to leave comments about any future topics you like covered – I’d particularly like ideas for more Flashback to Basics Fridays. If I choose your idea, perhaps I’ll even find a way to get you some cool Synopsys swag…
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.