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First PCIe 5.0 32GT/s PHY IP
Posted by Scott Knowlton on December 19, 2018
Richard has been talking about how long it’s been since he’s posted. I have to say, it’s been forever since I’ve posted a blog and I’ll need to work on that in 2019. Yes, I’m still alive and kicking and so much has happened since I’ve posted. More on that in another post.
The PCIe 5.0 specification from PCI-SIG is now at 0.9 (which Richard mentioned in his last post). Also, in Richard’s last post, he was showing eye diagrams from an early PCIe 5.0 prototype that we had. I’m writing this post to show you the latest eye diagram from our brand new DesignWare PCIe 5.0 32GT/s PCIe PHY in N7 that we just got back from the fab a few days ago. Everything is looking great so far …
DesignWare PCIe 5.0 PHY at 32GT/s
We have many customers already designing in our DesignWare IP for PCI Express 5.0 PHYs and Controllers to build amazing products for ADAS, AI, Networking and Servers. Please leverage our expertise and knowledge in PCIe and PCIe 5.0 (along with our IP) to help you get these incredible products to the market.
Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.
Regards,
Scott
PS: To everyone out there – I wish you Happy Holidays!
Scott KnowltonI started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard. I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.
Richard Solomon
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.