Posted by Richard Solomon on November 28, 2018
No, no, “it” does NOT refer to “get Richard back on the blog after some 4 months of silence” – although I think Scott was starting to think that and was probably considering threats of bodily harm!
I know there was a LOT of (very well justified, I have to confess) skepticism when the PCI-SIG announced PCIe 5.0 back in June of 2017 and claimed the spec would be “completed in 2019”. Scott talked about this a little while after that year’s Developers Conference and noted that Synopsys had already demonstrated PCIe 5.0 running 32GT/s in simulation.
One of my excuses for not blogging much lately is the raft of PCI-SIG Developers Conferences – the most recent one being in Taiwan. Here you can see me showing off the Synopsys PCIe 4.0 complete system with what we call “RAS-DES” and which I covered in my “PCIe Designs for Automotive Applications” presentation.
The other demo Synopsys was showing there in Taiwan was this one:
Yes, that’s a very nice eye diagram coming out of a prototype PCIe 5.0 32GT/s “Gen5” PHY which you can see in the foreground on the right! Those of you with good eyes will notice the displays off to the left are for the Synopsys Verification IP for PCI Express 5.0…
I’ve talked for ages about how many engineers Synopsys has committed to various PCI-SIG workgroups for protocol, electrical, and compliance – and I talk to many of those folks on a fairly regular basis. So I have been in a great position to keep tabs on the PCIe 5.0 development, and I’ve been very confident that the PCI-SIG has been executing to a MOST aggressive schedule since that first announcement.
While in Taiwan, I got the opportunity to speak on behalf of the PCI-SIG to a number of press folks, and try to convey to them my enthusiasm for PCIe 5.0 and my confidence in its unprecedented schedule. I’ll have to defer to my multi-lingual readers to confirm it, but I’m told that I was at least partially successful as CTIMES and EE Times Taiwan both covered PCIe. (I actually spoke to a very sharp EE Times Japan reporter as well who took LOTS of pictures, so I hoped she would publish something too, but I’ve not seen it happen yet.)
Today I am extremely happy to say all the hard work of hundreds of engineers around the world from Synopsys and many other companies has paid off! PCI-SIG members should have seen an email announcement last night or this morning that the Draft 0.9 Revision of the PCI Express 5.0 Base Specification was released for member review!
As long-time ExpressYourself readers will know, once a PCI-SIG specification goes to Draft 0.9, there are no functional changes allowed, so the “official” final “1.0” release will follow after the member IP review period closes. (Just as PCIe 4.0 did previously.) So while it’s possible that some catastrophic event might happen, or some terrible error have been overlooked by the thousands and thousands of person-hours of reviews already, I am quite confident the final PCIe 5.0 release will in fact be released in 2019 – just as PCI-SIG said it would less than two years ago! (Bonus points if it comes out on or before my birthday…)
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I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.