Posted by Richard Solomon on June 18, 2018
Whew, what a week! That’s another PCI-SIG Developers Conference in the books though.
I was just in sunny Santa Clara (California of course) discussing all things PCI Express® technology with more than 560 PCI-SIG® members from around the world. Our members come together to learn from the PCIe® experts leading the spec development work as well as from companies that are implementing the technology now.
The conference included 4 tracks of presentations over two days, all given by engineers from PCI-SIG member companies, and covering all the hottest PCI Express topics—from the latest on PCIe 5.0 technology to an update on the M.2 form factor to lessons learned by early PCIe 4.0 adopters. An open panel discussion with the PCI-SIG work group chairs gave attendees the opportunity to get answers to their most pressing PCIe-related questions.
For the first time ever, all the presentations were video recorded. So yes, if you missed Devcon or just weren’t able to attend all the sessions you wanted to, you should very soon be able to watch the videos. Having all these PCI Express experts onsite and with the video folks already here as well, the PCI-SIG kicked off a new educational video series, covering topics such as the PCIe technology ecosystem, low power features, and more. Yes, that’s me looking sooooo comfortable in front of the camera! Stay tuned for the videos to be posted shortly – and these should be available to everyone including non-PCI-SIG members.
It’s awesome to see that PCI Express is continuing its dominance as the industry’s leading I/O technology and there is a lot to look forward to. We have seen rapid adoption of PCI Express 4.0 technology in 2018 alone, with numerous announcements from PCI-SIG member companies releasing PCIe 4.0-based products at DevCon.
During DevCon, the PCI-SIG also announced the publication of PCI Express 5.0, Version 0.7, with Version 0.9 releasing on its coattails later this year. We are targeting Q1 2019 for completion of the PCIe 5.0, Release 1.0 specification, further solidifying PCI-SIG’s track record of doubling I/O bandwidth every three years.
Don’t worry if you missed the PCI-SIG Developers Conference; you can catch PCI-SIG at other events across the globe this year. In October, there will be additional DevCons in Israel and APAC and various PCI-SIG folks will be speaking at industry events including the Flash Memory Summit in August.
Thank you all again for making this a great event!
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.