Posted by Richard Solomon on April 30, 2018
Well things are about to get busier – though given I got off a plane Thursday night from the PCI-SIG Compliance Workshop #105 and got on another one less than 12 hours later to go to a family wedding… Perhaps my definition of “busy” is a bit suspect!
In any case, there’s a full slate of PCI-SIG Developers Conferences coming up over the next several months. I’m just putting the finishing touches on the Synopsys PCIe 5.0 demo for next month’s PCI-SIG European Developers Conference (at this point, it’s also next WEEK’s conference – eek). European folks may recall we last had one of these back in 2012, so I hope you will all help get the word out and get enough attendance that we can increase the frequency of these European events! Even if you haven’t registered in advance, you can still show up onsite and register there. (Do bring a company ID or business card or similar to make registration quicker and easier.)
Please bring a friend (or ten!) to come get the latest info on PCI Express, and stop by the Synopsys booth to say “Hi”!
For those of you in the USA, get the US Developers Conference (June 5-6) on your calendar and consider registering now:
Given how fast PCI-SIG is moving on PCIe 5.0, this years’ Developers Conferences should be “Don’t miss!” events for everyone doing PCIe design! Fear not, there are also DevCons scheduled for Israel, Taiwan, and Japan – all in October (did I mention “busy” earlier?).
I hope to see you all at one of these!
P.S. We’ve got a new piece of software which goes through all the old blog posts looking for broken links. Let me know in the comments if you think it’s better to leave links to no-longer available external content (e.g. IDF) or to delete them…
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.