Posted by Richard Solomon on September 1, 2017
“What’s in a name? that which we call a rose by any other word would smell as sweet”
How many times do you get Shakespeare in a tech blog? Well, here at ExpressYourself we like to cover all the bases 🙂 (I’m fond of announcing that “I have a poetic license and I’m not afraid to use it!” much to the chagrin of my children I’m sure.)
Actually though, I’m going to take a slight issue with ole William on this one – because another of my sayings is that “Words have power!” By that I mean it’s important to be precise with language and actually use the correct words for things. It’s true then, that Humpty-Dumpty and I probably would not have gotten along terribly well…. “What does any of this have to do with PCI Express?” you may be asking by now.
Well, it seems like every PCI Express IP provider claims to have a “Root Complex” so let’s see what that really means. A Root Complex is the source of a PCI Express hierarchy. If you picture what I call an inverted tree, where the root is at the top, and the hierarchy fans out wider and wider as you go down, the Root Complex is the highest-up element on that tree. Another way to think of it is that a Root Complex contains the first piece of PCI Express logic encountered by a transaction from the system CPU.
According to the PCI Express Base Specification, the Root Complex is responsible for all sorts of things:
Back on the subject of PCI Express hierarchies, I should point out that Root Complexes are permitted to have multiple ports on them for fanout, and that Switches are defined to expand those ports even further. Note that a Switch by definition doesn’t implement the Root Complex logic, it just passes along transactions it gets from a Root Complex above it.
While the specification doesn’t actually *require* a Root Complex to have a CPU, or even be connected to one, it’s really the only practical option. One could conceivably implement a slew of state machines to perform all the required tasks in hardware, but I don’t know of anyone who thinks that would be a good idea! Especially since the various operating system vendors and communities have put a lot of work into implementing as much of these features in software as they can. As part of verifying that these things work, the PCI-SIG performs compliance testing on Root Complexes as part of a “motherboard” which includes a CPU, firmware, and an operating system. Only by successfully passing those dedicated tests at a PCI-SIG Compliance Workshop, and successfully interoperating with the Switches and Endpoints scheduled with it at that workshop, can a Root Complex be listed on the PCI-SIG Integrator’s List.
You might recall that back in mid-2015 we here at Synopsys showed off a complete PCI Express 4.0 system running 16GT/s (“Gen4”) made up of our Root Complex and Endpoint IP implemented in hardware, along with our PCIe 4.0 16GT/s PHY test silicon.
The demo showed a complete Root Complex, including the Synopsys ARC CPU, a full Linux implementation, and everything needed for compliance testing at a PCI-SIG Compliance Workshop. (Note the date stamp from YouTube on the video – it seems like the word “first” is confusing for some IP vendors who’re announcing being first with PCIe 4.0 in 2017!) In fact, we took that same hardware setup to PCI-SIG Compliance Testing and got on the PCI-SIG Integrator’s List for PCIe 3.0 8GT/s Root Complexes. Notice that at the time of this blog posting, there aren’t any other IP vendors listed for Root Complex. I’ve linked to Root Complexes sorted by date in case one of them later does get on the Integrators List and claims to be first with that. 🙄
“But Richard, why aren’t other IP Vendors on the list?”
Well, I can’t speak for them, but this brings us back around to the point that a piece of PCI Express IP which implements the Root Complex configuration space is necessary but not sufficient to be a Root Complex. As should be obvious, a PCI Express Switch placed beneath a PCI Express Root Complex isn’t itself a Root Complex either. Maybe the answer is “Because they don’t have all the pieces they need to do that testing.”
So if you hear someone touting their PCI Express Root Complex IP as being “used for testing at PCI-SIG Compliance Workshops” but they don’t have a complete PCI Express Root Complex, you can rest assured it’s not being “used” in the way they’d like you to think! Details of what happens at those workshops is confidential*, but I can tell you that Synopsys has brought their PCI Express 4.0 16GT/s Root Complex and Endpoint to all of the PCI-SIG events doing pre-FYI and FYI testing for PCIe 4.0, and we intend to continue doing so at least until those tests are official and there is a PCIe 4.0 Integrators List. We continue to evolve our system through the draft PCIe 4.0 specifications, so multiple different implementations can be tested.
If you have any more topics you’d like to see covered (either as “Flashback to Basics Fridays” or otherwise), please comment below! As always, please subscribe to ExpressYourself by clicking here for RSS or here for email so you don’t miss out on any future updates!
*I can confirm that Synopsys engineers have been using what we call the “RAS DES features” built in to our PCI Express IP to help customers, fellow travelers, *AND* our competitors debug PCIe 4.0 16GT/s connectivity because we firmly believe that interoperable devices are critical to the continued success of PCI Express.
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.