Posted by Scott Knowlton on August 15, 2017
At the PCI-SIG DevCon in June 2017 two announcements were made with regards to PCI Express specifications. The first is that the specification for PCIe 4.0 is now at version 0.9. The second and even more interesting announcement was of the new PCI Express 5.0 specification at the initial 0.3 version. With the PCI Express 5.0 announcement, the industry gets another doubling of speed from 16.0GT/s to 32GT/s per lane providing a bandwidth for a x16 (16 lanes) at about 128GB/s. The chart below provides a comparison for the different generations of PCIe rates and bandwidth.
The intent with the new PCIe 5.0 specification is to minimalize the changes to enable the specification to proceed quickly through the specification process. In fact, the schedule being driven into the working groups is very aggressive, especially if you compare to what we seen for the releases of the PCIe 4.0 specification. The initial 0.3 version of the PCIe 5.0 specification confirms the intent for minimal changes in features, so most of the work to update the controller will be to support the double data rates.
Synopsys has a long history of providing several PCIe IP “firsts” enabling our customers to develop SoCs with the latest (and I’d say best) PCIe interfaces to meet their aggressive rollouts while utilizing the latest PCIe technology. Beginning with the first day of the conference, on June 7, 2017, Synopsys was showcasing our support for PCIe 5.0 in our booth. In case you were not able to come to the show, you can see the video that we recorded of the First Demonstration of PCI Express 5.0 at 32GT/s.
Users of the Synopsys DesignWare Controller IP for PCIe 5.0 can leverage our coreConsultant interface to easily change the configurations of their PCI Express interface to evaluate tradeoffs between performance and costs. This architectural exploration can be performed at your desk without the need for changes from a far off factory. A video showcasing the benefits as presented by Richard is shown below. Of course, this is PCIe 4.0, but PCIe 5.0 is just an extension of this process and behaves the same way.
Of course, this is the first version of the specification and there are always developments and challenges that add to the schedule and release of the new specification and products associated with it. Some things that come to mind:
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I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.