Express Yourself

At the PCI-SIG DevCon in June 2017 two announcements were made with regards to PCI Express specifications. The first is that the specification for PCIe 4.0 is now at version 0.9. The second and even more interesting announcement was of the new PCI Express 5.0 specification at the initial 0.3 version. With the PCI Express 5.0 announcement, the industry gets another doubling of speed from 16.0GT/s to 32GT/s per lane providing a bandwidth for a x16 (16 lanes) at about 128GB/s. The chart below provides a comparison for the different generations of PCIe rates and bandwidth.

The intent with the new PCIe 5.0 specification is to minimalize the changes to enable the specification to proceed quickly through the specification process. In fact, the schedule being driven into the working groups is very aggressive, especially if you compare to what we seen for the releases of the PCIe 4.0 specification. The initial 0.3 version of the PCIe 5.0 specification confirms the intent for minimal changes in features, so most of the work to update the controller will be to support the double data rates.

Synopsys has a long history of providing several PCIe IP “firsts” enabling our customers to develop SoCs with the latest (and I’d say best) PCIe interfaces to meet their aggressive rollouts while utilizing the latest PCIe technology. Beginning with the first day of the conference, on June 7, 2017, Synopsys was showcasing our support for PCIe 5.0 in our booth. In case you were not able to come to the show, you can see the video that we recorded of the First Demonstration of PCI Express 5.0 at 32GT/s.

Users of the Synopsys DesignWare Controller IP for PCIe 5.0 can leverage our coreConsultant interface to easily change the configurations of their PCI Express interface to evaluate tradeoffs between performance and costs. This architectural exploration can be performed at your desk without the need for changes from a far off factory. A video showcasing the benefits as presented by Richard is shown below. Of course, this is PCIe 4.0, but PCIe 5.0 is just an extension of this process and behaves the same way.

Of course, this is the first version of the specification and there are always developments and challenges that add to the schedule and release of the new specification and products associated with it. Some things that come to mind:

• At 32GT/s, what is the new channel going to be?
• What changes will be required for the connector to support 32G?
• Will the PIPE I/F change? Of course, the PIPE specification isn’t a PCI-SIG specification, but for those of us providing or using IP, PIPE is an important specification to connect PHYs with Controllers. Whatever changes come with the PCIe 5.0 specification, we look forward to being on the journey with you.

Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.

Regards,

Scott