Posted by Richard Solomon on November 16, 2016
Ok, so the title reference might be a bit aged for many of our readers… You young-uns can check out this YouTube video for a hint. On the offhand chance that you missed the email from PCI-SIG, I’ll give a (PCI-SIG members-only of course) link directly in to the new 0.7 Draft of PCI Express 4.0: https://members.pcisig.com/wg/PCI-SIG/document/download/9977
Actually the “new phonebook’s here” is not the worst analogy I’ve ever come up with, since just like Navin, getting this spec draft into print is both a big deal and not. Certainly we’ve all been waiting for this draft to finally *officially* be released – and waiting for much longer than anyone hoped it would take. On the other hand, all the major features have been settled for ages. PCI-SIG has publicly announced things like Lane Margining at the Receiver, options for increased flow control credit, and options for additional transaction tags. So just as Navin didn’t suddenly spring into existence when he was “published” in the phone book, neither did the 0.7 Draft. I guess I’d better cut the analogy off here before one of you smart alecks starts drawing conclusions about the PCIe spec based on the rest of the movie 😀 (Oh, and just in case you were wondering, yes, these features are already available in the Synopsys controller IP!)
Yes, yes, I’ve already heard the “It’s 1400 pages!” wailing – and I do want to point out that if you read none of the rest of the 0.7 Draft, please read the very first page (before the title page even). Within those several paragraphs is one (just before the Note to Reviewers) which mentions the possibility of an important change which may come with the 0.9 Draft. (Details of this have NOT been made public by PCI-SIG, so I can’t talk about it more here.) Personally I think that change would simply be a reflection of reality and would be a good thing for the industry to formalize, however please do look and especially if contrarian, provide your opinion back to the PCI-SIG in your feedback on the 0.7 Draft. (Feel free to also send me a comment either here or via email but make sure PCI-SIG knows how you feel about that direction.)
Based on questions I’ve gotten recently, I should point out (especially for folks seeing this feature for the first time) that “Lane Margining at the Receiver” is *NOT* about measuring the PCIe *receiver*, it’s about measuring the actual *channel*. The early versions of this feature were called “Receiver Margining” which explains some of the confusion, and the name change was adopted in an attempt to help clarify things. This one *HAS* been discussed publicly by PCI-SIG, but Richard’s short version explanation is this:
With Lane Margining, the root complex instructs a PCIe device to shift its receiver’s sampling point left and right (in time) and/or up and down (in voltage) in an attempt to find the limits of the actual signal eye arriving at that device.
Remember that the transmitted signal and the channel each meets certain specifications in order to ensure a particular minimum amplitude and width of the signal eye at the receiver. Receivers are specified to be able to resolve that minimum eye, so Lane Margining has *NOTHING* to do with whether anything is “compliant” or not. What Lane Margining can do is provide an idea of how close to “the edge” a particular system is. System manufacturers could use it to check that a particular batch of PCBs is still meeting spec, or find out how close a system is to falling below the legal eye minimum.
Enough for now, happy reading! If you’d like more info on anything from the Draft 0.7 or have any more topics you’d like to see covered (either as “Flashback to Basics Fridays” or otherwise), please comment below! As always, please subscribe to ExpressYourself by clicking here for RSS or here for email so you don’t miss out on any future updates!
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.