Posted by Richard Solomon on August 17, 2016
Scott and I are out at IDF (Intel Developer Forum – not the Tavor-wielding IDF) this week, where the keynote yesterday was all about Virtual Reality, Augmented Reality, and Merged Reality …. oddly not much was said about plain old real reality. If you missed us last week at Flash Memory Summit (FMS) please stop by Booth #230 and say “Hi”. Heck, even if you didn’t miss us, come by anyway! Speaking of FMS, I should first give you an….
I apologize for not posting sooner, but after spending so much time last week chanting under my breath my favorite old Polish folk-saying (“Not my circus, not my monkeys!”) I was struggling with exactly what to post about FMS. Suffice it to say that there were a number of logistical “challenges” with the show itself – culminating in a no-show of the moderator for the PCIe/NVMe session. However, I did have a good turnout of 50-60 folks for my session on using PCIe 4.0 in SSDs. I really appreciated everyone’s patience as the speakers worked out our own lineup and introductions (and no, for the record, despite how I introduced him, Debendra didn’t *actually* invent a banana peeler). There was definitely a lot of interest in PCIe 4.0 from SSD folks and that was evident in our booth traffic as well. This shouldn’t be surprising to anyone given new technologies in non-volatile media and the relative ease of aggregating NAND (or other) chips to get extremely high bandwidth, not to mention that most common PCIe SSD form-factors are limited to 4 lanes. (Remember that SFF-8639, now sometimes called U.2, and the newish M.2 form-factor both top out at PCIe x4 configurations so their only real choice for more bandwidth is higher signaling speed.) Regardless of the hiccups, thanks for all those who stopped by – including some old friends and colleagues:
August has certainly been a busy month, so onward to…
I know, it’s a bit of a stretch to use the term “Real” around most things at a trade show 😀 I confess to being a bit underwhelmed by the various Virtual/Augmented/Merged Reality demos at the IDF keynote Tuesday. Maybe it’s the fact that the on-stage demo didn’t seem to track the demonstrator’s walking very well, or maybe it’s that the “Merged Reality” video would have required an immense physical space throughout which the protagonist would move. (Actually Sci-Fi fans might recall that the main character in the Empire of Man series gets injured during some Virtual Reality training when he runs up against a physical barrier not comprehended/anticipated by the programmer of the training scenario. As Prince Roger learns there – it can really stink when Real Reality trumps Virtual Reality!)
I am impressed by how much compute, graphic, and sensor resources Intel has crammed into their self-contained Virtual Reality headset. Anyone who’s still questioning whether PCIe makes sense in mobile-type applications should realize from this application that mobile and low-power don’t necessarily mean low-bandwidth!
I’ve noticed that there are still a lot of folks at these events who are not aware of just how far along PCIe 4.0 has come. Perhaps they’re being swayed by the near-FUD coming out of some prognosticators who say PCIe 4.0 is years away from fruition, or perhaps they just don’t subscribe to ExpressYourself, but I keep encountering engineers who are surprised to find that PCIe 4.0 (prototype) devices are here with us in Real Reality today. Scott and I are showing the World’s First Multi-vendor PCIe 4.0 Interoperability again – where attendees can see our PHY and Controller IP interoperating with Teledyne-LeCroy’s Exerciser/Analyzer. This is two completely independently-developed PCIe 4.0 implementations working together at 16GT/s!!! I know I’m a techno-geek, but seriously – that’s awfully darn Real Reality for a spec some people keep insisting is “years away!”. For those that may have missed the demos so far (at PCI-SIG Devcon US in June, FMS last week, or IDF this week) you can now see a video made by our colleague Torrey:
If you do make it out to IDF this week, please stop by and say “Hi” to Scott and me, and as we pretty much always ask, please subscribe to ExpressYourself by clicking here for RSS or here for email so you don’t miss any future updates or opportunities to hassle us!
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.