Posted by Richard Solomon on June 21, 2016
Hopefully all of you have made plans to attend this year’s PCI-SIG Developers Conference (aka Devcon) next week in Santa Clara. This is THE event to learn about PCI Express technology, and network with your fellow PCIe ecosystem members. Of course Synopsys will be there, both on the exhibition hall floor and in the Member Implementation tracks. Come listen to the big dogs from Synopsys R&D teach you (and our competitors) about two important topics. First, come by Track 3 on Tuesday at 3:30pm to hear how we got our DesignWare Root Port IP for PCI Express on the PCI-SIG Integrator’s List as the first *EVER* from an IP provider! Don’t miss the 10:30am Wednesday morning session (also in Track 3) on PCI Express in automotive applications. Yes, it’s true, I’m taking a bit of a rest on this one and “only” presenting PCI-SIG sessions this time, but the other Synopsys presenters will keep you informed, even if they’re not as funny as I think I am 😀
See the full conference agenda at: http://pcisig.com/pci-sig-developers-conference-2016-agenda. If you thought I was just being snarky about teaching our competitors, check out their abstracts, and compare those against some Synopsys presentations from years past…. PCI Express 16GT/s Design for Reliability, Replay and Debug of Post Silicon Bugs in Simulation, PCI Express Controller Design Challenges at 16GTs, and a few more from 2014 and earlier which I can’t get to at the moment. Speaking of big dogs, be sure to attend the “PCIe 4.0 Panel Discussion” Tuesday at 4:30pm where you can ask questions of the PCI-SIG workgroup chairs and other members deeply involved in the PCIe specification development.
I hope you will all come by the Synopsys booth and see something I’ve just been bursting to tell you about! You know that way back in 2014 we were the first to show a 16GT/s PCIe PHY and show simulations of a 16GT/s controller (Summer Blockbusters Featuring Gen4, Gen3 and M-PCIe) and of course, we introduced the World’s First PCIe 4.0 System in June 2015, followed quickly by the World’s Second PCIe 4.0 System in November 2015. Now that we’re midway through 2016, it’s of course time for another PCIe 4.0 first…. Oh, I probably shouldn’t say, and you should come by the booth to see it in hardware for the best effect.
What? You’re not going to Devcon???
Oh, you are but you’re just impatient! Ok, that I get! Plus I’ve never been accused of being patient. Here you go: buried inside today’s Synopsys Press Release on latency improvement is this
“Synopsys’ DesignWare PHY and Controller IP for PCI Express 4.0 technology has been tested for interoperability using the Teledyne LeCroy Summit Z416 Protocol Analyzer/Exerciser, which is targeted to test for PCIe 4.0 compliance in the near future,” said John Wiedemeier, product marketing manager at Teledyne LeCroy. “This is an important indicator to all designers and the ecosystem that the DesignWare IP works as expected and meets the latest PCI Express specification requirements, mitigating risk and accelerating time-to-market.”
Wait a minute Richard, do you mean to tell me you’ve now got FULL interoperability with someone else’s PCIe 4.0 implementation? And that someone is a test-equipment vendor dedicated to checking that you’re following the spec?!??!
Yep! It’s really better seen in action, so come run with the leader of the big dogs – because otherwise the view doesn’t change much! 😈 (Don’t worry, we’ll get a Youtube video out there soon so even those poor souls not making it next week will be able to see too.)
If you do make it over to Devcon, stop by and say “Hi” to Scott and me, and as we always ask, please subscribe to ExpressYourself by clicking here for RSS or here for email so you don’t miss any future updates.
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.