Posted by Richard Solomon on April 7, 2016
“What’s this?!?!? A blog posting from Richard? Wasn’t he killed in a fiery camel-riding crash at the last PCI-SIG Israel event or something?”
Sigh. I know, I know, I’m waaaaaaaaaaaaaaaay overdue for paying attention to the blog. Even the Synopsys folks who maintain our blog infrastructure thought I’d fallen off the face of the earth. Luckily the rumors of my demise are greatly exaggerated…
…as all of you who came out to my presentation at SNUG Silicon Valley would have realized! I was a little worried at first when one of the event organizers told me that we were set up in “the ballroom”. As soon as I got onsite I realized the room is a ballroom in name only – it’s probably only capable of holding a hundred people or so. Nonetheless, I was encouraged to see all the ExpressYourself readers had turned out in force. Ok, well, maybe not ALL of the attendees were ExpressYourself readers – but hopefully they will be by now 🙂
In any case, I went through a quick update on PCI Express 4.0 (more on that later here) and talked about some of the challenges design teams will face implementing the new 16GT/s (aka “Gen4”) signaling rate. I also spent a good bit of time talking about what we’re calling “Design For Reliability” – which is an approach to building RAS (Reliability, Availability, Serviceability) features into controllers. Enterprise-class devices have long insisted on RAS Data Protection features like memory and datapath error detection and correction. Especially with “Gen4” rolling out to early adopters, and the industry gearing up for a new PCIe data rate, I think it’s going to be super-critical to have good debug features built in as well. I’m not sure when or if we’ll have the SNUG slides online, but those of you who are PCI-SIG members can also check out my past presentations (such as this one from Devcon 2015) for some details on the topic.
Naturally, the easiest way to get all these great RAS features *TODAY* is in a PCI Express solution from Synopsys. We know that you’re going to have to interoperate with lots of different components though, some of which might even be from other PCIe IP providers, so we think it’s worthwhile to get this information out to the whole industry. Now that we’ve educated them, look for our competitors to start touting similar features soon! 😀 Hey, aside from imitation being the sincerest form of flattery, it will be good if you have a way to definitively prove to your PCIe link partner that IT’S NOT YOUR FAULT!
Of course no discussion of PCI Express 4.0 is complete without at least one person asking “When is the spec going to be out?” Well, that’s it, I’ve gotta run…. Sigh, no seriously, Scott is always giving me grief about this topic too. I point out that PCIe 4.0 is going to have a whole bunch of material incorporated which readers used to have to go find in things like the “Classic” PCI specification. I point out that we’ve added a few new features, and that the 0.7 draft is likely to be the most complete such revision in the history of PCI-SIG. Nobody cares, they just want a date. If I’m really unlucky, they point out that I might have said something about March in the past. Because this is a public blog, I really can’t even speculate out loud – but I can point out that the next PCI-SIG Developers Conference is coming up at the end of June.
“Surely,” I might say, “the PCI-SIG would have a new spec draft in its members’ hands for a month or two before their premiere training event!”
Oops, did I say that out loud?
Thanks again for following us here at ExpressYourself, I promise (again) to be better about blogging from here on out. Don’t forget that Scott and I are always looking for comments with any insights YOU have or topics you’d like to hear about and as always, please subscribe to ExpressYourself by clicking here for RSS or here for email so you don’t miss any future episodes. Be careful on those camel rides!
P.S. No animals were harmed in the making of this blog post!
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.