Posted by Scott Knowlton on March 4, 2016
The video at ARM TechCon of our 2nd PCIe Gen4 system got kind of lost in our end of the year, Thanksgiving, Christmas, New Years, End of the 1st Quarter rush. I know that my videos of PCIe won’t win any Oscars, but one wonders if someone is just hiding this masterpiece from the public eye. Ok, ok, it’s not a masterpiece, but I’m sure folks would like to see PCIe 4.0 in action. Just for fun, see if you can find my mistakes! There are at least 5!
Richard pointed out in his last blog posting, as you may recall, the world’s first PCIe Gen4 system is comprised of a Synopsys PCIe Gen4 Root Complex talking to a Synopsys PCIe Gen4 Endpoint (both of which have passed PCI-SIG compliance testing at Gen3 by the way). This second PCIe 4.0 demo utilizes a PCIe switch to connect to an existing PC and do translation between PCIe Gen2 and PCIe Gen4 speeds. The block diagram looks like this:
Of course, we have a real picture of the hardware to go with the block diagram:
The lost video you’ve been waiting for, ok maybe not waiting, but turn the lights down and have a view:
The PCIe 4.0 specification was announced on November 29th, 2011 and we are still only at the 0.5 revision of the specification. Of course, we have PCIe4.0 customers that are already designing their next generation systems using our DesignWare PCIe 4.0 controllers and PHYs. Why don’t you join us?
Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.
If you do try to find all my mess-ups, leave me a message and I’ll come up with a prize for the winner! Synopsys employees – go ahead and try, but no prizes for you.
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.