Posted by Scott Knowlton on June 22, 2015
There will be many demos at PCI-SIG 2015 this week declaring readiness for PCIe 4.0. Synopsys is one of them and will be showing PCIe 4.0 controllers, PHYs and verification IP. Of course, it’s great that the industry ecosystem is gearing up to support PCIe 4.0, but the specification is still under development and we have a way to go before PCIe 4.0 is finalized.
The PCIe 4.0 specification was announced on November 29th, 2011 and we are still only at the 0.5 revision of the specification. Of course, I have customers that are getting impatient on how long it is taking for the specification to move forward and I have customers that are happy with PCIe at 5.0GT/s. For those pushing the boundaries of speed into a new frontier using the latest, smallest geometries – It’s going to be fun and we look forward to our continued partnership!
If you’re pushing the reliability and/or speed of your next generation system, you may want to review the Synopsys PCI Express announcement that went out today. “Synopsys PCI Express IP Adds System-Level Data Protection Features for High-Performance Cloud Computing SoCs”. Some of the highlights:
In the latest release of our PCIe controllers, we have beefed up our data protection mechanisms to support the demanding requirements of super-fast computing, networking and storage (systems and SSDs). We’ve always had data protection support in our controllers, but the faster speeds and the smaller geometries have customers pushing for increased functionality and options for data protection. Along with the increase in data protection features, we have added several new features to help our customers debug their systems when something goes wrong during silicon debug, testing error conditions for their software or while the system is running. We have also added ways to monitor system activity statistically and through event monitoring. All of these features are being used by our customers to improve the reliability, availability and serviceability (RAS) of their systems. We hope you find these features useful for your next designs.
Of course, not to forget Gen4 at 16GT/s, the Synopsys Controllers and PHYs also support the latest PCIe 4.0 v0.5 specification.
If you’d like more information on what types of RAS features are interesting in the PCIe interface, you may want to stop by and hear Richard’s presentation at PCI-SIG 2015. Below is the abstract and more information.
PCI Express 16GT/s Design for Reliability
PCI Express 4.0’s upcoming 16GT/s speed offers data rates well above the frequencies of the ubiquitous microwave oven! Today’s designers have a number of unique challenges to design, debug and test their SoC’s before the product can go into mass production. Some of these challenges include multiple passes of equalization, understanding and tracking link reliability, determining/proving system-level reliability, and on top of it all the reawakening of long-dormant concerns about on-die soft errors due to shrinking silicon geometries. This presentation will discuss several features and techniques that SoC designers can use to design for higher chip reliability and observability.
Presenter: Richard Solomon
Date/Time: Tuesday, June 23, 1:00-2:00 pm
I hope to see you at PCI-SIG 2015. Stop by the booth and say hi and/or see our latest PCIe 4.0 demos.
For more information on the Synopsys PCIe solutions, please visit our web site.
Feel free to comment or provide suggestions on any topic that you’d like Richard or myself to discuss.
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I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.