Posted by Scott Knowlton on June 22, 2015
Richard and I will be at PCI-SIG. For any of you that go to PCI-SIG, you know Richard will be doing several presentations, some for PCI-SIG and some for Synopsys, so you can find him walking around. For me, you’ll be able to find me in the sessions or at the Synopsys booth during the exhibit times. Catch us or stop by the booth and tell us about your latest PCIe projects. Both of us love to hear about the latest ways you’re using PCI Express in your designs. We also like it when you tell us you read the blog.
Of course, you’d expect a leader in PCI Express to be showing some cool demos and we will. PCIe 4.0 will of course be the highlight as it was for us last year. We continue to make progress even while the PCIe 4.0 spec is slowly moving forward…
Stop by the Synopsys booth to see demonstrations for:
In addition, Synopsys and Keysight Technologies will show the industry’s first PCIe 4.0 system level link simulation vs. measurement correlation demonstration at the Keysight Technology booth.
I know you come to the booth for the cool demos, right? Well, just in case you come to PCI-SIG just to hear Richard’s jokes and not our demos, we are also giving away cool Star Wars themed USB sticks if you watch the demos and you could ultimately win a Parrot AR Drone Quadricopter 2.0!
We have technical papers in the sessions that you don’t want to miss.
PCI Express 16GT/s Design for Reliability
PCI Express 4.0’s upcoming 16GT/s speed offers data rates well above the frequencies of the ubiquitous microwave oven! Today’s designers have a number of unique challenges to design, debug and test their SoC’s before the product can go into mass production. Some of these challenges include multiple passes of equalization, understanding and tracking link reliability, determining/proving system-level reliability, and on top of it all the reawakening of long-dormant concerns about on-die soft errors due to shrinking silicon geometries. This presentation will discuss several features and techniques that SoC designers can use to design for higher chip reliability and observability.
Presenter: Richard Solomon
Date/Time: Tuesday, June 23, 1:00-2:00 pm
Replay and Debug of Post Silicon Bugs in Simulation
PCIe core designers have to balance verification completeness with time to market constraints. It is impossible to fully validate a PCIe core especially when one considers the possibility of real world issues that present themselves outside of the PCIe functional specification. Given certain issues will be uncovered post silicon whether in the lab or in a customer’s hands there is the need to easily replay the condition in simulation where the issue can quickly be debugged. This session will cover how through simulation with verification IP, error conditions can be replayed in simulation through both automated and user controlled techniques allowing for the possibility of replaying almost any scenario seen in silicon. The session will also address how source based compliance tests can be enhanced to prevent the future introduction of such bugs.
Presenter: Paul Graykowski
Date/Time: Wednesday, June 24, 1:30-2:30 pm
Enabling Complex PCI Express 4.0 Design Validation
Increasing pressure for faster time-to-market in complex designs using PCI Express 4.0 and other high data rate interfaces has spurred the need for quick and accurate link performance validation. IBIS Algorithmic Modeling Interface (IBIS-AMI) has become well known as a common and efficient validation methodology by both system developers and SerDes IP providers across different standards. In this presentation we will explain what an IBIS-AMI model is, how we incorporate circuit simulation results into the model, and demonstrate the accuracy of the approach by comparing IBIS-AMI simulation results to silicon measurements for a 16 Gbps PCIe 4.0 link.
Presenter: Pegah Alavi, Keysight
Date/Time: Tuesday, June 23, 10:30-11:30 am
On last thing before I go. Richard said he’d do a dance up on stage if there was 50% voter turnout in the recent PCI-SIG elections. I’m not sure if that happened, but I suggest that everyone chant DANCE, DANCE, DANCE at the end of his opening session on Tuesday. Let’s get him to dance up on stage and please make sure it ends up on YouTube!
For more information on the Synopsys PCIe solutions, please visit our web site.
Feel free to comment or provide suggestions on any topic that you’d like Richard or myself to discuss.
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I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.