Posted by Scott Knowlton on May 21, 2015
First, I’m sure there are some of you that look at this and think “what the heck”? PCIe being used in phones and tablet devices? How can that be? Rest assured PCIe has been used in mobile devices for a long time. Of course, laptops have been using it, but it’s also being used in phones and tablets for some time now. You may remember that PCIe with the MIPI M-PHY and say, that’s what Scott’s talking about, but no. This is the full blown PCI Express in these devices operating at 5.0GT/s and 8GT/s.
Who wants to put a PCIe PHY developed for driving backplanes and across multiple connectors into a phone? Good question! The ability to do this really comes down to managing the power in the PHY and controller in coordination with the rest of the chip design connected to a small channel. Of course, L1 substates was a huge stride to get you there, but the power needs to be reduced even further. Nobody wants their phone or tablet using up power when you are not using it, just to be dead when you need it. The interface needs to be completely off and this can be done when using L1 substates in conjunction with power gating techniques.
If you are developing applications, especially battery based applications that require low-power, you should take a look at our announcement today “Synopsys Announces Industry’s Lowest Power PCI Express 3.1 IP Solution”. Some highlights from the press release:
While any application can benefit from using a low power PCIe solution, battery powered mobile devices tend to gain the most with the Synopsys PCIe solution. Our customers are looking to lower the power in both active and standby modes enabling the prolonging the battery as much as possible.
For more information on the Synopsys PCIe solutions, please visit our web site.
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I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.