Posted by Richard Solomon on April 10, 2015
Yes, yes, I know that I’ve been saying for months that we’d see the next draft (0.5) of PCIe 4.0 “soon”. Yes, I know that “soon” is not usually considered “3-4 months” – but in my defense, remember that we’re talking about standards here…. and hitting the same year as originally promised is often considered above-average performance 🙁
Because this is a public blog and open to non-PCI-SIG members I can’t go very deeply into the details of what’s in draft 0.5, but I can suggest that everyone download it. Pay particular attention to the first page “Open Issues” and “Anticipated changes that reviewers should be aware of”. None of these should be particularly surprising (and I’ve talked about some of them at PCI-SIG Devcon before) but they’re good heads-up items. Of course most of the changes are in Chapter 4 (PHY Logical) and Chapter 9 (Electrical) – though I’ll note that the electrical chapter doesn’t yet include results from the two PHY test vehicles (here’s a hint as to their identities – they demonstrated interoperability at PCI-SIG Israel last month). To save you some trouble finding the downloads (especially if you happen to be reading this after the review period closes), here are the links for the changebar and non-changebar versions. Both the protocol and electrical workgroups would very much like your feedback, so please do take some time to go through this draft and return comments before May 11. If you have opinions on those Open Issues (and here’s a hint – you should!) then I especially encourage you to provide feedback.
For those of you attending the upcoming PCI-SIG Compliance Workshop (#93) the week of April 21-24, I expect to be around the first couple of days so feel free to track me down and say “Hi”. Hmmm, maybe I should come up with a special prize for the first ExpressYourself reader to find me onsite and tell me the altitude shown on my GPS picture from last month’s posting.
Speaking of upcoming events, I hope everyone here has the US Devcon dates marked on their calendar! (That’s June 23-24, still at the Santa Clara convention center.) I’ve heard from a few of the workgroup chairs that they have more new PCIe 4.0 information to present, so there should be a lot more than just electrical “stuff” on the PCIe 4.0 front this year. Of course this is open only to employees of PCI-SIG member companies, but a) if you’re doing any kind of PCI Express development you really SHOULD be a PCI-SIG member and b) people have been known to join PCI-SIG just to hear my jokes during the presentations*. While I recognize that not too many of our non-US readers get the opportunity to come to US Devcon, please keep an eye on the PCI-SIG Events page – I think folks in Asia will be very happy this October! For those in Europe looking for a local event, especially if you missed the Israel Devcon, my best advice is to email PCI-SIG administration (yes there’s a real email address, yes you already have it, but NO I won’t post it here for joyful consumption by SPAMbots) and request one. (I suggest offering to bring 100 of your closest friends.)
As always, thanks for following us here at ExpressYourself and please feel free to leave us comments on what you think of Draft 0.5 (of course send detail feedback to PCI-SIG, but tell us how you really feel). If for some crazy reason you haven’t already done so, please click here to subscribe to ExpressYourself so you don’t miss anything.
*Ok, so that’s an obvious lie 🙂 On the other hand, I promise a very special gift to the first person who can prove their company newly joined PCI-SIG and put “We want to hear Richard’s jokes at Devcon” down on the application!
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.