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Back to school and PCIe 4.0 “secrets”
Posted by Richard Solomon on September 15, 2014
Now that my kids are back to school, things are calming down slightly. Well, ok, the chaos is shifting gears 🙂 I’m still recovering from IDF last week, and I owe you all a blog post about that, but I’ve been remiss in advising you of how you too can get “back to school” … with an upcoming Webinar on challenges you’ll face in PCI Express 4.0 design.
This Tuesday (16-September) at 11am Pacific, I’ll be talking through some key things PCIe 4.0 designers will need to know. There’s been a lot of talk about the PHY and electrical side of the upcoming specification, so I’ll mostly be focused on the controller side.
Here’s a quick teaser on the topics:
- How the specification recommends handling re-drivers and retimers
- Design changes to consider to handle new specifications on link equalization and the PHY interface
- How multiple packets per clock cycle will affect designs using PCIe 4.0
- Questions to ask for effective implementation of 16GT/s
So if you’re not too busy tomorrow (yes, I know, short notice!) please signup and follow along:
http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=synopsys_sep1614
[EDIT: Use this link to view the webinar after the fact http://webinar.techonline.com/19027]
Sorry for the short notice (and short posting) – I’ll make it up to you with another “contest” perhaps. Note that I only had 2 winners last time, so your odds are excellent. Of course, the prizes might leave a little to be desired 😀
Thanks,
Richard
Scott KnowltonI started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard. I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.
Richard Solomon
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.