Posted by Richard Solomon on September 15, 2014
Now that my kids are back to school, things are calming down slightly. Well, ok, the chaos is shifting gears 🙂 I’m still recovering from IDF last week, and I owe you all a blog post about that, but I’ve been remiss in advising you of how you too can get “back to school” … with an upcoming Webinar on challenges you’ll face in PCI Express 4.0 design.
This Tuesday (16-September) at 11am Pacific, I’ll be talking through some key things PCIe 4.0 designers will need to know. There’s been a lot of talk about the PHY and electrical side of the upcoming specification, so I’ll mostly be focused on the controller side.
Here’s a quick teaser on the topics:
So if you’re not too busy tomorrow (yes, I know, short notice!) please signup and follow along:
[EDIT: Use this link to view the webinar after the fact http://webinar.techonline.com/19027]
Sorry for the short notice (and short posting) – I’ll make it up to you with another “contest” perhaps. Note that I only had 2 winners last time, so your odds are excellent. Of course, the prizes might leave a little to be desired 😀
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.