Posted by Scott Knowlton on June 2, 2014
As I put the final touches on preparations for the PCI-SIG Developer’s Conference and getting ready to show you multiple demos for our recently announced support for PCI Express 4.0 there are exciting developments happening from Synopsys that will make your next SoC design easier. Let’s face it. Your goal is to build a product and there are multiple steps that have to be completed before the product is done while doing this under increasingly shorter time to market goals. This means that we are trying to do as many tasks as possible in parallel and they need to stay coordinated. Today, Synopsys announced our new IP Accelerated Initiative that focuses on enabling designers to incorporate IP into your SoC design flow at multiple levels of the design process by using a coordinated solution between IP prototyping kits, software development kits and customized IP subsystems.
The new DesignWare IP Development Kits provide a proven reference design for the IP preloaded onto a HAPS-DX prototyping system and a software development platform running Linux OS with reference drivers.
SoCs contain multiple protocols and interfaces and the IP Accelerated Initiative supports the protocols that Synopsys offers. The IP Accelerated Initiative will help the designer using our DesignWare PCI Express IP by providing a software development platform and reference design along with our PCI Express IP that all coordinates together enabling concurrent software and HW development.
The last part of the IP Accelerated Initiative is to enable rapid customization and integration of the IP into the design. When I first started working at Synopsys in the IP group, we were working to convince people that using IP was a good thing. In talking to our customers, they all knew how to design the blocks for the protocols we were producing, so they would look through your code and architecture to see if it was better than theirs and it wasn’t just a make verse buy decision. Those days are past and purchasing IP is standard practice. The interesting side effect today is that designers are losing the expertise to implement the whole interface protocol on their chip as they move on to other portions of the SoC where they add higher value for their company. This is forcing a rethinking in the industry and customers are no longer looking to buy a PCIe PHY and PCIe Controller and put them together themselves for their SoC. Companies are looking to buy the whole interface from their IP vendor, but since it’s far more complicated than just stitching the two blocks together, the last part of the IP Accelerated Initiative focuses on delivering the full interface (in this case PCIe) to the customer with the customization and specific configuration needed for the SoC. Of course, this is carried further providing additional customizations, integration and verification based on the customer’s needs in order to get their SoC out the door.
If you’re at PCI-SIG this week, stop by our booth and say hello, discuss the IP Accelerated Initiative and see some great demos for our PCI Express 4.0 solutions. If you missed any of the press announcements you can view them here:
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I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.