Posted by Richard Solomon on April 30, 2014
Sorry, I’ve been very delinquent in posting – it’s been a busy month! As you might guess from the title, one of the things keeping me busy was doing last year’s income taxes. (Non-USA folks might not know the dread with which Americans approach April 15th each year – the day our income taxes are due.) Changing employers of course complicated things a little (apparently I managed to overpay Social Security) and I was lucky enough to have some nice gains in the stock market. Unfortunately I had some nice gains in the stock market so I went from filling out the “send us most of your money” tax forms to the “send us all your money” tax forms. A time-honored American tradition is finding legal ways to manipulate money so as to pay less in taxes – apparently I’m not very good at this!
Ok, Ok, I know you’re thinking “Stop your whining Richard, this has nothing to do with PCI Express!”
Ah, but it does! You see, one of the questions I get asked ALL THE TIME (especially by people new to or not familiar with PCI Express) is “Why are you PCI Express people having such a hard time with X Gb/s when <some other standard> is doing 2X or 10X Gb/s already?” The answer has EVERYTHING to do with “taxes” albeit in a manner a little different than a Federal Form 1040.
In this case, the “tax” is really a question of who pays for the extra speed. In a PCI Express system we’ve got a chip providing the Root Complex, some interconnect (PCB, likely a connector, another PCB), and another chip serving as the Endpoint. (You can of course add switches, and soon “extension devices“, to your heart’s delight, but the same “taxation” equation applies between them.) The same general architecture applies in many of these other standards (Ethernet, SAS, etc) but what you will usually find is that the costs of higher speed in those standards get spread more evenly – specifically to the interconnect portion. Have you priced a 12G SAS cable lately? (Probably not, given the spec isn’t out – but have you priced a 6G SAS cable even?) If you “tax” everyone in the infrastructure “equally” then the “pain” of a new implementation is spread pretty evenly.
PCI Express doesn’t work this way. Maybe it’s more “American” in this sense 🙂 One of the code-words you’ll hear from PCI Express folks is “High Volume Manufacturing (HVM)”. Here’s a hint, HVM means “cheap”! The thought process is somewhat tied to traditional PC type systems – where every system includes PCI Express slots, but not every slot in every sold unit gets used. In fact, most slots sold go empty. Regardless, for PCI Express, the focus is on reducing manufacturing cost for the entire system. The theory is that silicon costs are one-time (you pay mostly for the R&D, the actual additional silicon cost for a more capable SERDES is small) but interconnect manufacturing costs are every-time (more expensive PCBs cost you in every unit sold). In other words, PCI Express taxes the silicon more heavily than the interconnect in order to help the overall system pay less of a “speed tax”.
Are you with me so far? So what we get with PCI Express is largely the same interconnect as we had with PCIe 1.0 – a bunch of really cheap (oops, I mean “High Volume Manufacturable”) FR4 PCBs with no fancy impedance matching, no fancy layer-to-layer connections, nothing at all which isn’t “HVM”. In electrical terms that results in channels which are, to quote Synopsys Fellow John Stonick, “really ugly!” This puts a tremendous burden on the silicon side – the transmitter and receiver, aka the PHY or SERDES in each and every PCI Express chip. Instead of getting to tax the interconnect like those other standards do, the PCI Express spec is forced to make its speed increase almost entirely in the transmitter and receiver.
So next time you’re around someone who’s bemoaning the delays in PCIe 4.0’s 16GT/s “Gen4” signaling and they wonder aloud “Why can’t those PCI Express guys get that spec done…” feel free to tell them the same thing I do:
“It’s something to do with avoiding taxes!” 🙂
Once again, thank you for reading ExpressYourself and in order to avoid the wrath of the IRS, click here to subscribe to this blog! Any non-SPAMbots reading this are also encouraged to leave me a comment with advice on how to reduce one’s income tax, or I suppose a PCI Express topic you’d rather read about in a future blog posting.
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.