Posted by Richard Solomon on March 31, 2014
Well, I should know better, but in my New Year’s Resolution post I said “Those of you who are PCI-SIG members should soon see what PCI-SIG calls the ‘0.3 draft’ of PCIe 4.0…” Sigh. Did I say “soon”? I meant, “eventually” – oh crud, no, let’s be honest, I meant “soon”. If truth be told, I really thought “soon” would be before the end of Q1 … yeah, I know, that’s today…thus this blog posting.
Partially that’s because ever since PCI-SIG started putting out these 0.X drafts, the 0.3 of any specification has been little more than “We’re thinking about doing some new stuff, like A, B, and maybe C, unless you like D – which we might do if enough of you want it”. The standard for releasing a 0.3 is pretty low, it needs to have:
Historically 0.3s have looked kinda like this one – a previous spec with a few pages of changebar material thrown in. So given that, you can see why I and others would expect PCI Express 4.0 Draft 0.3 to be a pretty quick drop – “Take PCIe 3.0 and run it twice as fast”. Things didn’t quite work out that way. There were some miscommunications within the PCI-SIG workgroups as well – one group sent its part of the spec for cross-workgroup review labeled as if it were the complete 0.3, etc, etc… All the same kinds of things that go wrong with “real” projects in your own company go wrong with standards organizations. Add in a 100% volunteer “workforce” all of whom have “day jobs” – usually in design and development, and you’ve got a perfect recipe for schedule creep.
The good news is that this time around, the 0.3 draft is going to actually be a draft – as in the specification in early form, not just an old spec with some very small amount of new material stuffed in here and there. We’re building on top of the PCI Express 3.1 specification, so 4.0 in all its drafts will look like a logical progression – because it will *BE* a logical progression!
“Whoa, hold it right there Mister!” you’re probably thinking about now “PCI Express 3.1 isn’t even out yet!!!“
Ah, yeah, there’s that too. Since we’re building atop 3.1, we kinda have to get 3.1 perfect and released before we can get the first 4.0 draft out. Again, all goodness in terms of getting a really solid spec, but all the time you can just hear Marvin saying “Delays! Delays!” can’t you?
Did I mention PCI-SIG has a new team of tech writers, who were volunteered by their company? So add in a learning curve to all the above, and toss in a ton of legacy documentation in old formats which aren’t very friendly to large documents. (I’m not going to name any names but if you’re thinking of a common word processor whose name rhymes with “bird” you’re probably dead on.)
Sorry, I guess this has ended up a lot more like a “dog ate my homework” posting than I really planned on, but at least the PCI Express 4.0 Draft 0.3 should wow you when it finally comes out … soon. <Ducking>
If I’m wrong this time around, then Marvin will likely blast me with his ACME Disintegration Pistol in sheer frustration.
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I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.