I was in Los Angeles, California visiting a friend that has been working in the movie business and it reminded me about the videos that we shot at PCI-SIG of the M-PCIe demos. After doing a few short videos over time, I have a whole new respect for the actors and actresses that make movies. It’s not as easy as it seems. At the beginning of the video “Industry’s First GEAR3 M-PCIe and M-PHY Demo”, I’m shrugging my shoulders after being told to loosen up and they caught that on tape and it’s now part of our demo. I have a hard time believing that was the best take and I’m going to have a conversation with the editing department! You should see the blooper reel they made as they turned this into a dancing Scott. Scary, very scary.
Wow, I feel all official and everything now that my name is up in genuine electrons here! First I am compelled to correct Scott… I do have an appreciation for red wine. Without it there would be no red wine vinegar – which goes great on fries (chips for my EU friends)!
For some of you, you may ask “who is Richard Solomon”, others may ask “what were you thinking”? Richard is currently the Vice President of the PCI-SIG board, the governing body for PCI/PCI-X/PCI Express specifications and 90 days have already passed since Richard joined us here at Synopsys as a Technical Marketing Manager for PCI Express. We are excited to have him here and be a contributer to our PCI Express team and the great products that we produce.
In my last post, I discussed highlights from the recent 2013 PCI-SIG Developer’s Conference including PCIe 4.0, OCuLink and M-PCIe. I also provided information on the world’s first M-PCIe interoperability demo, which showcased M-PCIe solutions from Intel and Synopsys working together. I concluded with the promise of information on the second M-PCIe demo from Synopsys and more information on M-PCIe.
I’ve just spent the last couple of days at PCI-SIG’s DevCon and all I can say is WOW! I’ve been working with PCIe since 2003 and have been to every PCI-SIG Developer’s Conference since then. I don’t recall there ever being one with such a high level of excitement and large attendance as this one. I’m sure this DevCon had record attendance.
Posted in Architecture, General Protocol, Low Power, M-PCIe, M-PHY, Market Adoption, MIPI, NVM Express, PCI Express, PCI-SIG, SATA/SATA Express, SCSI Express/SOP/PQI, Specification, Uncategorized | Comments Off on PCI-SIG DevCon 2013: PCI Express Everywhere!
While PCI Express has been the dominant interconnect for chips that target personal computing, digital home, server, storage and networking applications, it has yet to be popular in products for the mobile market. Battery based devices like tablets and smartphones have ultra-low power requirements, placing a completely different emphasis on PCI Express. Great strides have been made to reduce power in the PCI Express protocol, with enhancements like half-swing drivers, Dynamic Power Allocation (DPA) controls, Latency Tolerance Reporting (LTR), Optimized Buffer Flush/Fill (OBFF) and the relatively new power-saving L1 Substates. However, the challenges of driving PCI Express’ high data rates across 16” to 20” server channels have kept the power requirements of the PCI Express PHYs well above what mobile devices can tolerate. If PCI Express was ever going to extend into the world of ultra-low power mobile devices, something drastic would have to be done.
For each new generation of PCI Express, it takes time for the final version of the specification to be available. For PCIe 3.0, the protocol was changed to double the effective bandwidth over the previous version (Gen2) even though the rate only increased from 5.0 GT/s to 8.0 GT/s. This protocol change plus the addition of the equalization protocol to support the new Decision Feedback Equalization (DFE) made the transition to PCIe 3.0 much more complex and consequently extended out the availability of the final 3.0 specification. Of course, this also had an impact on the arrival of products in the market.
Synopsys is hosting our annual user’s group meeting (SNUG) at the Santa Clara convention center this week. Within SNUG we feature an IP Summit which includes presentations and tutorials on many of the IPs that Synopsys offers. In this year’s SNUG, we have eight in-depth technical sessions on PCI Express, 10G SerDes, FinFETs, DDR4, embedded memories and standard logic libraries and more. If you haven’t already registered, you can register on-site and it’s free! To see what’s happening at the IP Summit, you can use the IP Summit at-a-glance here: http://www.synopsys.com/IP/Pages/ipsummit2013.aspx
For over nine years, our customers have successfully implemented Synopsys’ DesignWare® PCI Express IP into their SoCs. We just announced the new DesignWare Enterprise 10G PHY. The 28-nm PHY is multilingual, speaking PCI Express 3.0, 10GBASE-KR, 10GBASE-KX4, 1000BASE-KX, CEI-6G-SR, SGMII and QSGMII and supports data rates from 1.25Gbps to 10.3Gbps per lane. With support for the IEEE Energy Efficient Ethernet (EEE) standard, the PHY’s low power consumption targets a wide range of green, high-end networking and computing applications
Happy New Year everyone! I wish you and your loved ones the best for 2013.
Posted in Uncategorized | Comments Off on Welcome to 2013!