Posted by Scott Knowlton on August 8, 2013
I was in Los Angeles, California visiting a friend that has been working in the movie business and it reminded me about the videos that we shot at PCI-SIG of the M-PCIe demos. After doing a few short videos over time, I have a whole new respect for the actors and actresses that make movies. It’s not as easy as it seems. At the beginning of the video “Industry’s First GEAR3 M-PCIe and M-PHY Demo”, I’m shrugging my shoulders after being told to loosen up and they caught that on tape and it’s now part of our demo. I have a hard time believing that was the best take and I’m going to have a conversation with the editing department! You should see the blooper reel they made as they turned this into a dancing Scott. Scary, very scary.
In my previous blog posts, I went through the two demos that we did for PCI-SIG in June. In the posts, I had some pictures of the demos, but it’s still not the same as watching a video to get the flavor of the demo. After all, “Seeing is Believing!” and this is the first interoperability demo between two companies’ M-PCIe solutions.
This first video is “Intel and Synopsys: Industry’s First M-PCIe IP Interoperability Demonstration”. You can read the technical details of the demo and see pictures in the previous post “PCI-SIG DevCon 2013: PCI Express Everywhere!” Click on the graphic below to watch the video.
The second video is “Industry’s First GEAR3 M-PCIe and M-PHY Demo”. You can read about the technical details of the demo and see pictures in the previous post “PCI-SIG DevDon 2013: M-PCIe with M-PHY Shifts into GEAR 3“. Click on the graphic below to watch the video.
For more information on Synopsys’ M-PCIe solutions, you can visit our web site for additional information.
As always, we’d love to hear from you on the value of these posts and any ideas that you’d like for Richard or I to talk about.
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.