Posted by Scott Knowlton on June 27, 2013
I’ve just spent the last couple of days at PCI-SIG’s DevCon and all I can say is WOW! I’ve been working with PCIe since 2003 and have been to every PCI-SIG Developer’s Conference since then. I don’t recall there ever being one with such a high level of excitement and large attendance as this one. I’m sure this DevCon had record attendance.
In thinking about why there was such an increase in the attendees this year, I think it comes down to two things:
Truly, it is PCI Express Everywhere.
If you missed the show, here are a few things for you. Of course, no one would accuse me of being biased in my blog for Synopsys or for PCI Express; wink, wink.
One of the first questions I’m asked from customers about PCI Express is when is PCIe 4.0 @ 16GT/s (Gen4) going to be available? My crystal ball isn’t too reliable – just take a look at my stock picks, but I digress… PCI-SIG in their keynote did provide some insight on their target dates and provided the following guidance:
That said, targets are targets and we will have to wait and see if PCI Express 4.0 comes out on this timeline. We can also expect a release of the PCI Express 3.1 specification which is a roll up of the errata and ECNs to the PCI Express 3.0 specification to happen in 2013.
PCI Express is also focusing its reach outside the box with OCuLink. This enables 1, 2 or 4 lanes of PCI Express 3.0 connectivity to an external device. The cable can be passive copper or an active implementation over either copper or optical. If you are already using PCI Express for your chip to chip and have it on the board, why would you need USB 3.0, NextGen USB or Thunderbolt? Reduce your costs and just move to OCuLink!
In my opinion, the big news at this PCI-SIG DevCon was M-PCIe. The M-PCIe ECN was finalized last week and already there were three presentations on M-PCIe (officially, I’m told, it’s not called Mobile Express or Mobile PCI Express, but just plain M-PCIe) and multiple demos in the exhibit area with hardware running M-PCIe. The first of the presentations was from Mahesh Wagh of Intel, who presented to a standing room only audience, even after adding two more rows of chairs. Synopsys had two demos in our booth running M-PCIe. Our first M-PCIe demo was the world’s first interoperability demo between M-PCIe solutions brought to you by Intel and Synopsys. After all, you can prove that you can talk to yourself, but what good is a new standard if you cannot talk to others. Aren’t people that talk to themselves a bit crazy?
There are no systems out there that have a M-PCIe Root Complex, so to demonstrate M-PCIe interoperability between Synopsys and Intel, we designed a system that uses a standard PC, a PCIe to M-PCIe switch and a M-PCIe Endpoint device with USB 3.0. We had to come up with a way to showcase the interoperability between our solutions while also showing that M-PCIe is still using the standard PCI Express protocol. The picture below is the Intel/Synopsys interoperability demo hardware incorporating a Synopsys HAPS FPGA-based Prototyping Solution.
In this system, we are using the PCIe to M-PCIe switch to do the conversion to M-PCIe and then connecting the downstream port of the switch to our M-PCIe Endpoint device. Of course the PC and operating system doesn’t know that we have moved from PCIe to M-PCIe and using an M-PHY for the link and new LTSSMs, so the Window’s Device Manager just reports a standard PCI Bridge device and our USB 3.0 PCIe Endpoint. A shot of the Device Manager is in the screenshot below.
This is the world’s first Interoperability demo for M-PCIe components and the PC is unaware that we have changed PHYs. That’s just the way that it’s supposed to work.
In my next post, I’ll provide you with a walk through of our other M-PCIe demo and provide more information on M-PCIe. In the meantime, do what I did after the show – kick back with a glass of red wine and relax.
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.