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PCI Express with M-PHY: A Match Made in Heaven

While PCI Express has been the dominant interconnect for chips that target personal computing, digital home, server, storage and networking applications, it has yet to be popular in products for the mobile market. Battery based devices like tablets and smartphones have ultra-low power requirements, placing a completely different emphasis on PCI Express.  Great strides have been made to reduce power in the PCI Express protocol, with enhancements like half-swing drivers, Dynamic Power Allocation (DPA) controls, Latency Tolerance Reporting (LTR), Optimized Buffer Flush/Fill (OBFF) and the relatively new power-saving L1 Substates.  However, the challenges of driving PCI Express’ high data rates across 16” to 20” server channels have kept the power requirements of the PCI Express PHYs well above what mobile devices can tolerate.  If PCI Express was ever going to extend into the world of ultra-low power mobile devices, something drastic would have to be done.

In 2012, Synopsys joined a group of like-minded PCI Express technology leaders to determine how to reduce power in PCI Express and bring its protocol, programming models, and wide spectrum of designs to the mobile space.  Ultimately the group decided to completely replace the “legacy” PCI Express PHY and use the MIPI Alliance’s M-PHY due to its proven power-efficiency and range of speeds.  In September of 2012, the PCI-SIG and MIPI Alliance announced their collaboration to enable SoC designers to easily move existing PCI Express interfaces to the new M-PCIe specification with little or no change to their existing PCI Express infrastructure and software.  Work proceeded quickly and by early 2013 the two groups announced the first version of the M-PCIe Engineering Change Notice (ECN). Last week, the M-PCIe ECN was approved and is now a part of the PCI Express specification

The diagram below shows a comparison of PCI Express on the left to the new M-PCIe on the right. In order to maintain the PCI Express software programming models, the Transaction Layer (TL) and Data Link Layer (DLL) are unchanged between the two. This also allows for the application interfaces when moving from PCIe to M-PCIe to stay the same. With M-PCIe using a MIPI M-PHY, the PHY interfaces need to change. The M-PHY uses the RMMI interface, while the PCIe PHY uses the PIPE interface, which of course, necessitates changes to the LTSSM in the Logical PHY Layer (LPL) to support RMMI and the M-PHY.

PCI Express Comparison to M-PCIe

The use of the M-PHY with PCI Express enables developers to leverage all of the benefits of the PCI Express protocol with the lower power benefits of the M-PHY. The M-PHY doesn’t have to drive long trace lengths because it is used in mobile applications and the entry and exit latencies into low power modes are much better than a PCIe PHY with L1 sub-states.

Synopsys is announcing our DesignWare M-PCIe products at the PCI-SIG developer’s conference today. Our M-PCIe solution is based on our leading PCI Express solution, which has been is used in over 750 designs.

Customers using Synopsys’ PCI Express Controller IP can quickly migrate to M-PCIe, while keeping their investment in the existing application interfaces, RAMs and software. Since the changes in the controllers are focused in the LPL to accommodate the M-PHY, there is little risk in using the new DesignWare M-PCIe controllers.

If you’re at PCI-SIG on June 25th or 26th, come by the Synopsys booth and see our M-PCIe solutions in action.

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