Posted by Scott Knowlton on November 4, 2012
Why 4? PCI-SIG announced last November the fourth generation of the PCI Express specification operating at 16GT/s providing twice the throughput of PCI Express (PCIe) 3.0. This is the fourth generation of a standard that has replaced PCI, PCI-X and AGP to become the de-facto interconnect in digital office, servers, networking, digital home, storage and is quickly improving its position in mobile as well. BTW: What’s a MIPI?
If you haven’t seen the PCI Express 4.0 announcement, you can view it here:
As you’ve probably read my bio by now, I’ve been working with PCIe since 2003. The sheer number of PCIe customer designs that I’ve dealt with (over 650 controller designs to-date) gives me an interesting perspective on how designers are using PCIe in products. There are very distinct uses of the PCI Express interface. Designers that are building wireless hubs using PCIe have very different requirements than those building high-end computers and storage systems.
I’m constantly amazed at the speed at which this protocol changes to service its many markets. PCIe 1.0 (Gen1) brought us a serial protocol that moved the industry away from the problems of using parallel interfaces of PCI, PCI-X to give us more performance. However, Gen1 @ 2.5GT/s wasn’t fast enough for the graphics and server folks. It didn’t take long. Discussions started to provide an increase in performance and shortly an announcement for the next generation (Gen2) @ 5.0 GT/s was announced. Almost immediately, seemingly even before the spec was started, I was asked when I could deliver Gen2. We delivered, and delivered it early. It was clear though that the different market segments were moving at different paces. Those customers using PCIe for connectivity were moving at a different pace than the high performance computing crowd. Now, it seems that Gen1 is used less and less and customers have moved to Gen2 in the connectivity space, while the high performance types are moving on to Gen3. Gen3 is taking a while to digest due to the addition of the new equalization and the changes to the protocol, but products are out there and Gen3 saw a boost with Intel’s Ivy Bridge μPrelease. Now, on to Gen4 @ 16GT/s. Although PCI-SIG doesn’t release schedules, the first version of the PCIe 4.0 specification (0.3) is expected towards the end of this year. The performance treadmill keeps going and going.
As the speed continues to increase, the last year has seen a lot of activity to reduce power. As companies with a PC heritage move to bring tablets and ultrabooks to the market, they need to reduce the power consumption to extend battery life. This is for both active power and standby power. The first few changes were within the specification. These new features included the Optimized Buffer Flush/Fill (OBFF), Latency Tolerance Reporting (LTR) and L1 substates. Now, PCI-SIG is looking at using the MIPI M-PHY along with PCI Express to reduce the power consumption further. If you didn’t know that the MIPI and PCI-SIG organizations were talking, you should read this:
If you’re interested in more detailed information on some of the low power changes in PCI Express, you can read this article:
Yes, I do know what MIPI is. I worked on that for a while too.
I hope you come back to read further posts and Explore the world of PCI Express and its path to world domination; at least for chip interconnects …. And don’t forget your red wine. The Doctors say it’s good for you. Why should you argue with that advice?
Dr. Evil, you didn’t have a chance.
(For those of you that don’t know who Dr. Evil is, check out this YouTube video)
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.