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I wanted to title this “Upstream, downstream, in my lady’s chamber” in honor of the old nursery rhyme “Goosey, goosey, gander” – but after reading what Wikipedia has to say about the nursery rhyme it didn’t seem quite as childlike as I remembered… I also thought that putting “in my lady’s chamber” in a blog title was perhaps not going to show up on the kinds of google searches I’d actually hope for! I guess it’s all a matter of perspective.
At the PCI-SIG DevCon in June 2017 two announcements were made with regards to PCI Express specifications. The first is that the specification for PCIe 4.0 is now at version 0.9. The second and even more interesting announcement was of the new PCI Express 5.0 specification at the initial 0.3 version. With the PCI Express 5.0 announcement, the industry gets another doubling of speed from 16.0GT/s to 32GT/s per lane providing a bandwidth for a x16 (16 lanes) at about 128GB/s. The chart below provides a comparison for the different generations of PCIe rates and bandwidth.
Pop quiz! Which section of the PCI Express Base Specification covers bifurcation? Here, I’ll even wait while you look….
I’ve been thinking for a while (yes, that explains the burning smell) that we should be covering some of the basics of PCI Express here at ExpressYourself in addition to “just” the new stuff. After reading today’s posting, please let me know in the comments whether this is a good idea or not…
Ok, Ok, I confess to a bit of a sensationalist streak 🙂 [Who, me??] In truth, the world’s second PCIe Gen4 system is brought to you by the very same people who brought you the world’s first – us, Synopsys that is.
Unless you are Rob Ford of course, if you live in North America, you probably spent your Sunday morning much like I did – going around to every clock in the house and setting it an hour forward. If not, or if you ARE Rob Ford, then I’m sorry I didn’t post this blog entry on Saturday…
Wow, I feel all official and everything now that my name is up in genuine electrons here! First I am compelled to correct Scott… I do have an appreciation for red wine. Without it there would be no red wine vinegar – which goes great on fries (chips for my EU friends)!
Virtualization technology essentially componentizes a computer system into the following:
The PCI-SIG Compliance workshop #84 is taking place December 4-7 in Milpitas, California. At the workshop, you can test your PCIe 3.0 device as part of the “official FYI testing” to see if your product passes compliance. However, “FYI” testing is “For Your Information” and not “official testing”, so even if your product passes compliance you won’t be able to list it on the PCIe 3.0 Integrator’s list because this is only FYI testing. Based on the ramp for Gen1 and Gen2, I’d expect “official testing” for Gen 3 to begin by mid next year.
Scott KnowltonI started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard. I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.
Richard Solomon
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.