Custom Layout Insights: Analog/Custom Layout Blog

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HSPICE SIG event is here

I know HSPICE is not strictly a layout blog subject but for those of you who do the ‘Full Monty’ of design and layout consider going along to the SPICE/AMS event and check out the HSPICE SIG event. It’s at the Santa Clara Marriott Hotel on February 2nd (next Thursday). At this event, distinguished speakers from Xilinx, ARM, […]

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Trouble Ahead, Trouble Behind

There’s no doubt that FinFET technologies have been very appealing. With FinFETs being up to 37% faster while using less than half the dynamic power than planar transistors, they have been a ‘no brainer’ to adopt and the industry has embraced them. To that extent, in a recent survey of Synopsys users, more than a […]

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Reducing analog cell layout time with the symbolic editor.

In the last blog post I profiled the use of the symbolic editor for rapid digital cell layout. In this post we will tackle analog cell layout and show some more of the symbolic editor features that enable analog layout engineers to complete their layout in minutes versus hours. As with the digital cell layout, […]

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Rapid custom digital cell layout with the symbolic editor

In Custom Compiler Layout Assistants – part 1 we profiled the use of the symbolic editor and how it makes placing devices that need to be in a specific interdigitated pattern like for example a differential pair very easy. With no constraints to enter, no code to write, layout is done in minutes versus hours. […]

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Custom Compiler In-Design Assistants – part 3.

In the blog Custom Compiler In-Design Assistants Part 2, I outlined how we can use StarRC to report capacitances on critical nets in the layout even when the design is still in flux and not completely LVS clean. In addition to capacitance reports we also showed resistance reporting which is critical for FinFET based layouts. […]

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Custom Compiler at DAC 2016

  DAC 2016 saw the first Custom Design luncheon to feature Custom Compiler. It was a sold out event with 150 customer attendees eager to hear from Synopsys and other customers about how Synopsys is progressing in the custom design space. Antun Domic, Senior VP and General Manager of the Design Group moderated the event […]

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Custom Compiler In-Design Assistants – part 2

Planning which metal shape goes on which color (mask) is key when designing in a FinFET process, especially when propagating connections through the layout hierarchy. In addition, highly matched signals such as complementary clocks must be assigned to the same color, as routes on different masks have different resistances. So how do we ensure we […]

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Custom Compiler In-Design Assistants – part 1

On line Design Rule Checking (DRC) is nothing new. The technology has been in use for years in a variety of different layout editors and yet nearly every Layout engineer has a love / hate relationship with it. Why? Well it really comes down to the use model and the responsiveness of the application. At […]

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Custom Compiler Layout Assistants – part 2

In the last blog I detailed the symbolic editor layout assistant and showed how the layout engineer can make simple graphical choices of how the layout needs to look and then have the placement taken care of by a placement engine. In this post I will outline another layout assistant the router. The routing task […]

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Custom Compiler Layout Assistants – part 1.

On March 30th Silicon Valley was buzzing with excitement. Synopsys held the Silicon Valley SNUG event and revealed Custom Compiler, a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse. During the event the R&D folks did a walkthrough of the technology ‘under […]

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