Planning which metal shape goes on which color (mask) is key when designing in a FinFET process, especially when propagating connections through the layout hierarchy. In addition, highly matched signals such as complementary clocks must be assigned to the same color, as routes on different masks have different resistances. So how do we ensure we are keeping things in order with respect to the matching of resistance and capacitance?
On March 30th Silicon Valley was buzzing with excitement. Synopsys held the Silicon Valley SNUG event and revealed Custom Compiler, a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse. During the event the R&D folks did a walkthrough of the technology ‘under the hood’ and showed the audience some cool layout assistants that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.
Over the last series of blogs we have looked at what tools the layout engineer has available to him/her to help them deal with the complexity of doing layout with FinFETs. Even though there are tools that help, the fact is there is still a productivity hit when comparing the time it takes to do a FinFET based layout versus a planar CMOS layout. When I asked my layout colleagues “how much longer does it take to do a FinFET based design versus planar CMOS?” they said it takes 2-3X more time.