There’s no doubt that FinFET technologies have been very appealing. With FinFETs being up to 37% faster while using less than half the dynamic power than planar transistors, they have been a ‘no brainer’ to adopt and the industry has embraced them. To that extent, in a recent survey of Synopsys users, more than a third of those who responded plan to use FinFET technologies on their next chip.
Since its introduction the technology has been rapidly evolving. Take TSMC for example.TSMC’s 16FF+ (FinFET Plus) technology features FinFET transistors with a third generation High-k/Metal Gate process, a fifth generation of transistor strain process, and advanced 193nm lithography.
As a result, this latest 16nm technology offers substantial power reduction for the same chip performance. Now foundries are pushing even lower into 10nm and even 7nm process geometries.
In previous articles I outlined some of the many challenges that the first generation of FinFET technologies introduced into the custom layout flow. Many of you will be hitting these issues for the first time as 16nm and 14nm technologies move into the main stream. For those moving beyond the 16/14nm generation, there is trouble ahead as a whole new set of issues must be overcome.
For nodes below 16/14 we see new challenges related to design rules, layout effort, variation and analog/digital co-design. So for those taking the plunge to 10 nm and below, stay tuned as over the next few weeks I will unfold the gory details of these emerging challenges.
But that’s another post.