Custom Layout Insights: Analog/Custom Layout Blog

Archive for 2017


HSPICE SIG event is here

I know HSPICE is not strictly a layout blog subject but for those of you who do the ‘Full Monty’ of design and layout consider going along to the SPICE/AMS event and check out the HSPICE SIG event. It’s at the Santa Clara Marriott Hotel on February 2nd (next Thursday). At this event, distinguished speakers from Xilinx, ARM, Synopsys Mixed-signal IP Group, and Synopsys R&D will share their insights about using HSPICE to address some of the key challenges related to FinFET design and verification. Additionally, you will also have an opportunity to interact with Synopsys HSPICE R&D personnel as well as HSPICE Integrator Program (HIP) partners.

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Trouble Ahead, Trouble Behind

There’s no doubt that FinFET technologies have been very appealing. With FinFETs being up to 37% faster while using less than half the dynamic power than planar transistors, they have been a ‘no brainer’ to adopt and the industry has embraced them. To that extent, in a recent survey of Synopsys users, more than a third of those who responded plan to use FinFET technologies on their next chip.

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