Over the last series of blogs we have looked at what tools the layout engineer has available to him/her to help them deal with the complexity of doing layout with FinFETs. Even though there are tools that help, the fact is there is still a productivity hit when comparing the time it takes to do a FinFET based layout versus a planar CMOS layout. When I asked my layout colleagues “how much longer does it take to do a FinFET based design versus planar CMOS?” they said it takes 2-3X more time.
What is Electro-migration and why is it something we should care about?
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So, what tools do we have in our FinFET toolbox that can help layout engineers manage the complexity that FinFETs inherently bring?
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So, what do you have to do for routing? Well again, drawing on the experience of my layout colleagues who are still ‘in the business’ and dealing with FinFETs, here are a few landmines you will have to deal with.
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So, FinFETs rule! They give the designer so much flexibility in trading off power and performance that it should be a no brainer to adopt the technology – right?
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In my last post, I said ‘A hurricane has made land fall and its name is FinFET’. Ok, it’s a little corny, but it was not meant to convey a sense of impending doom for custom layout productivity.’ Hurricanes are no doubt disruptive, but humans can adapt to even the worst nature can bring. And FinFETs bring tremendous benefits along with the disruption.
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