Reducing analog cell layout time with the symbolic editor.
In the last blog post I profiled the use of the symbolic editor for rapid digital cell layout.
In this post we will tackle analog cell layout and show some more of the symbolic editor features that enable analog layout engineers to complete their layout in minutes versus hours.
As with the digital cell layout, the engineer can take advantage of the symbolic editor’s ability to define multiple P and N row pairs as shown in Figure 1.
Figure 1. Multiple row pairs.
The preview window shows how the layout will look when realized on the layout canvas. In this example, it is clear that in order to make the design more compact, the larger transistors need to be folded.
Folding the transistors is very easy using the symbolic editor. Options on the toolbar allow the designer to fold the transistor by specifying either the number of segments they want or by specifying a width threshold. Once the option is set, all the layout engineer has to do is simply select the appropriate devices and have them folded such that the transistors fit neatly in the rows. Figure 2, shows how the design looks before and after folding.
Figure 2. before and after folding.
Analog designs are very sensitive to process variation, noise and other manufacturing variances. In order to mitigate the impact of these variances on critical pieces of circuitry, layout engineers use complex inter-digitation patterns in addition to other layout techniques. This is a critical practice for analog design, because the effects of the variances, if not accounted for can lead to a nonfunctioning piece of circuitry.
The symbolic editor provides a simple way to implement these complex patterns via the Pattern Generator. As well as being able to specify your own patterns, the Pattern Generator also includes a library of built-in patterns that can be used to inter-digitate devices in a specific order. Take a differential pair for example. The layout engineer can choose from a variety of different patterns as shown in Figure 3.
Figure 3. Pattern generator.
The preview window makes it easy to see how the layout will look with the chosen pattern and once happy with the choice the engineer simply realizes the layout on the canvas. Figure 4 shows the results of choosing a Common Centroid pattern. With no constraints to enter, no code to write, layout is done in minutes versus hours.
Figure 4. Highlighted devices as part of a Common Centroid pattern.
Transistors are not the only devices that can take advantage of the symbolic editor. In the automotive world for example it is often necessary to layout banks of resistors. This is something that the symbolic editor can also help with. Resistors can be chained serially in a variety of different routing patterns.
Using the symbolic editor allows the layout engineer to make simple graphical choices of how the layout needs to look and then have the detailed placement taken care of by the placement engine. It makes it easy to add or remove placement rows and columns as well as insert dummy devices. Figure 6 shows the completed symbolic layout of two resistor banks with automatic insertion of dummies.
Figure 6. Completed symbolic layout of two resistor banks with automatic insertion of dummies.
Generating devices and placing them such that they meet all the design rules and produce a robust working design is about 30% of the layout time. Using a layout assistant like the symbolic editor really speeds this task up and makes the layout engineer much more productive. Synopsys (Laker) have invested heavily in this technology over a period of 5 plus years, such that it can address a broad range of design applications, unlike the recent offerings from other EDA vendors. Applicable to both FinFET and established planar CMOS nodes the symbolic editor makes analog cell layout quick and easy.
To learn more about how the symbolic editor can help to rapidly create analog cells, check out the video that shows the symbolic editor in action.
Next time we will take a look at Co-Design with Custom Compiler and IC Compiler.
Graham
Graham Etchells