Posted by Graham Etchells on September 30, 2016
In Custom Compiler Layout Assistants – part 1 we profiled the use of the symbolic editor and how it makes placing devices that need to be in a specific interdigitated pattern like for example a differential pair very easy. With no constraints to enter, no code to write, layout is done in minutes versus hours.
However, there is a lot more to the symbolic editor than the ability to simplify inter-digitation. One good example is the ability to define multiple P and N row pairs and then symbolically chain and fold the transistors such that you get them to fit neatly in the rows. This is a key feature that allows you to not only control the aspect ratio of the design, but to very rapidly create a custom digital cell layout, as shown in figure 1.
Figure 1. Multiple Row Pairs
The symbolic editor can also be used in conjunction with a cell template. The cell template provides a graphical way of defining the topology of your layout and in the case of digital standard cell design, provides a consistent base topology as the common starting point. With the cell template you can define where your power and ground rails are in relation to the P and N channels as well as the spacing between the P and N channels and other topology variables such as power and ground rail widths. The template can be modified to suit your needs and then saved off for future use by other layout designers.
Using the symbolic editor allows the layout engineer to make simple graphical choices of how the layout needs to look and then have the detailed placement taken care of by the placement engine. It makes it easy to add or remove placement rows and columns as well as insert dummy devices. Used in conjunction with the cell template, it is the fastest way to achieving correct layout of custom digital standard cells. Although it is particularly well suited for FinFET based designs it is equally as good on planar CMOS nodes. Generating the devices and placing them such that they meet all the design rules and will produce a robust working design is about 30% of the layout time. Using a layout assistant like the symbolic editor really speeds this task up and allows the layout engineer to boost productivity for the layout task as well as building a library of topologies for IP re-use.
To learn more about how the symbolic editor can help you to rapidly create custom digital cells, check out this video that shows the symbolic editor in action.
Next time we will take a look at how we can use the symbolic for analog cell design, but that’s another post.