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In advanced technology nodes, layout choices are increasingly influenced by challenges like parasitics, electro-migration (EM), and stringent design rules. Issues such as non-compliance with resistance or EM standards, and uneven capacitances in matched nets, can significantly delay layout schedules. Addressing these concerns early in the layout phase enables engineers to finalize designs more rapidly.
EM is especially problematic in FinFET processes due to the high performance of transistors and the use of thin metals. Consider, for instance, a layout engineer tasked with routing a critical net vulnerable to EM effects. This complex challenge, however, becomes more manageable with tools like Custom Compiler. It offers innovative features that simplify the process of designing interconnects that meet EM criteria.
One such feature is the interactive router, which allows for rapid routing of the target net. This intelligent tool also automatically connects the pins as the main line is extended. As a result, the task can be completed efficiently with just a few clicks. This is exemplified in figure 1.
Figure 1: Interactive router with automatic pin tapping
To identify electro-migration (EM) issues, the EM checker requires information about the currents on the pins. The layout engineer can easily provide this data by back-annotating the currents from a previous simulation run onto the pins. Once this is done, the next step is to select the recently routed net and activate the EM checker. The outcomes of this check are displayed in the electrical reporter pane, as illustrated in figure 2.
Figure 2: Electro-migration report
The EM report adopts a straightforward 'pass/fail' format. Nets that pass the check are highlighted in green, while those that fail are marked in red. For failing wires, the layout engineer can consult the report for detailed suggestions on the required wire width to rectify the issue. For example, in figure 3, the EM reporter indicates that increasing the width of metal 2 and metal 3 from .04 µm to .0505 µm would resolve the violations. Thus, a minor increase in interconnect width by .01 µm allows the engineer to effectively address EM concerns.
Figure 3: Recommended width to fix EM violations
Custom Compiler's Layout Assistant, with its interactive router, significantly eases this adjustment process. Utilizing the Track Pattern Assistant feature, the layout engineer can select the next suitable wire width for metals 2 and 3 that exceeds .0505 µm. As figure 4 demonstrates, the appropriate width is .06 µm.
Figure 4: Track Pattern Assistant
The process involves deleting the previously routed net with the old width and using the interactive router to swiftly re-route the net with the new .06 µm width. This tool automatically aligns the routing with the correct track and mask color. After re-running the EM report, all segments of the net now appear green, indicating compliance with EM rules.
Conclusion
In conclusion, managing the intricate challenges of advanced node design, particularly regarding parasitics, electro-migration (EM), and strict design rules, is crucial for efficient and successful chip layout. Early identification and resolution of issues related to resistance, EM criteria, and capacitance imbalances in matched nets are key to maintaining project timelines and achieving optimal design performance.
The utilization of advanced tools like Custom Compiler streamlines this process. With features such as the interactive router and the EM checker, layout engineers are empowered to quickly identify and rectify EM issues, ensuring that interconnects meet the stringent criteria required for advanced node technologies. The ability to easily adjust wire widths and reroute nets, as demonstrated in the examples provided, highlights the practicality and efficiency of these tools in addressing complex design challenges.
Ultimately, the integration of smart design tools and methodologies is not just a convenience but a necessity in the realm of advanced semiconductor design. By embracing these technologies, engineers can navigate the complexities of modern chip design with greater ease and precision, ensuring that the final designs are not only functional but also optimized for performance and reliability. This approach exemplifies the blend of innovation and practicality that is essential in the fast-evolving field of semiconductor design.
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