Custom Layout Insights: Analog/Custom Layout Blog

 

Custom Compiler In-Design Assistants – part 3.

In the blog Custom Compiler In-Design Assistants Part 2, I outlined how we can use StarRC to report capacitances on critical nets in the layout even when the design is still in flux and not completely LVS clean. In addition to capacitance reports we also showed resistance reporting which is critical for FinFET based layouts.  At advanced nodes, the impact of parasitics, electro-migration (EM) and restricted design rules, drive critical layout choices.  Interconnect that does not meet resistance or EM criteria and unbalanced capacitances on matched nets, can and often does adversely impact layout schedules. So the earlier in the layout phase, the layout engineer can address these issues, the sooner he or she can close the design.

EM in particular is a notorious problem in the FinFET process due to the high drive of the transistors and thin metals. So let’s say for example the layout engineer has to route a critical net which could be susceptible to the impact of EM. This is a non-trivial task that could be quite challenging. However, if you have Custom Compiler, there are some very cool capabilities that make laying out interconnect that meets EM criteria very quick and very easy.

First the interactive router can be used to quickly route the net in question and because this is a smart router the pins are tapped to automatically as the trunk is extended, so with only a few clicks the task is done.  See figure (1).

Start Route2_flightline

Figure 1. Interactive router with automatic pin tapping.

In order to check for electro-migration issues the EM checker needs to know what the currents are on the pins. To do this the layout engineer simply back annotates the currents onto the pins from one of the prior simulation runs. The next task is to select the net that was just routed and invoke the EM checker. The results are shown in the electrical reporter pane as shown in figure 2.

EM_1

Figure 2. Electro-migration report

The report is a ‘pass / fail’ style, where the nets shown in green are passing and those in red are failing. For wires that are failing the layout engineer can query the report to display additional information on what wire width would remove the violation. In figure 3, the EM reporter shows that if the wire width on metal 2 and metal 3 was .0505 µm instead of .04 µm the violations would be resolved. So by simply increasing the width of the interconnect by .01 µm the layout engineer can fix the EM issues.

EM_1_cropped

Figure 3. Recommended width to fix EM violations

Again, Custom Compiler’s Layout Assistant’s interactive router makes this task quick and simple. Using the Track Pattern Assistant, the layout engineer chooses the next available wire width for metals 2 and 3 that is greater than .0505 µm, which, as shown in figure 4 is .06 µm.

EM3_2

Figure 4.  Track Pattern Assistant.

The previously routed net with the old width is deleted and the interactive router is used to quickly re-route the net with the new .06 µm width which is automatically snapped to the correct routing track and mask color. When the EM report is re-run, all segments of the net are returned green indicating a pass for the EM rules.

So, although electro-migration can be a critical issue when dealing with FinFET designs, Custom Compiler’s In-Design assistant for EM reporting and the Layout Assistant for interactive routing make the task of dealing with EM simple and routine.

Check out this video link to see the In-Design Assistant electro-migration reporting in action.

http://www.synopsys.com/Tools/Implementation/CustomImplementation/Pages/custom-compiler-webisodes.aspx

Register here for a webinar on Custom Compiler.

https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1164103&sessionid=1&key=A22830ADCEAF97FC2377CA08BC24B737&partnerref=CC-blog

Next we will revisit the Layout assistant’s symbolic editor and highlight a few more cool features for planar CMOS designs.

But that’s another post.

Graham