Custom Layout Insights: Analog/Custom Layout Blog


Custom Compiler at DAC 2016


DAC 2016 saw the first Custom Design luncheon to feature Custom Compiler. It was a sold out event with 150 customer attendees eager to hear from Synopsys and other customers about how Synopsys is progressing in the custom design space. Antun Domic, Senior VP and General Manager of the Design Group moderated the event which included speakers from STMicroelectronics, GSI Technology, Samsung Foundry and the Synopsys IP team.

Antun opened the proceedings and presented Synopsys’ fresh approach to custom layout with Custom Compiler. He shared details of the pioneering visually-assisted automation technologies that speed up custom design tasks, reduce iterations and enable reuse.

Antun then went on to introduce each of the customer speakers who then proceeded to relate their experiences with Custom Compiler and how the visually assisted automation helped them reduce the layout effort from days to hours. First up was Atul Bhargava of STMicroelectronics.

Atul discussed why they deployed Custom Compiler for their 28nm FD-SOI IP designs. He highlighted how Custom Compiler assistants shorten layout tasks for memory and standard-cell design. In particular, Atul highlighted the value of the Symbolic Editor for the placement of their analog circuits. Another assistant they found very useful was Custom Compiler’s built in EM/R checking.

Next to speak was Randy You, CAD manager at GSI Technology. As a designer of high-speed SRAMs at advanced nodes, GSI products require high speeds and low power. Randy focused on how Custom Compiler enables them to design to those criteria and how Custom Compiler saves weeks of layout rework time. Randy also explained why the In-design DRC, EM checking and the matched length custom routing features in Custom Compiler were especially important for GSI.

Following Randy was Bonhyuk Koo from Samsung Foundry. Bonhyuk reiterated the challenges associated with FinFET design and highlighted that Custom Compiler is certified for Samsung’s 14nm process and that the 10nm certification will come in July.  The presentation covered several Custom Compiler enhancements, such as full coloring and fin grid snapping that make design at advanced nodes possible.

The final presentation was delivered by Phil Morris from the Synopsys mixed-signal IP R&D team. Phil gave an engaging talk on the collaboration between the Custom Compiler R&D team and the Synopsys IP team to tackle FinFET layout challenges. He shared an example of cutting a typical layout task from one hour to 8 minutes.

Videos of this event and the AMS event are available at the following link.