Custom Layout Insights: Analog/Custom Layout Blog


Custom Compiler Layout Assistants – part 1.

On March 30th Silicon Valley was buzzing with excitement. Synopsys held the Silicon Valley SNUG event and revealed Custom Compiler, a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse. During the event the R&D folks did a walkthrough of the technology ‘under the hood’ and showed the audience some cool layout assistants that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.

One of the layout assistants that was shown was the symbolic editor. This really is a must have assistant when it comes to placing devices that need to be in a specific interdigitated pattern like for example a differential pair. In the schematic it is two symbols but in the layout it could be hundreds of devices. The symbolic editor allows device placement to be edited in an easy and graphical manner and comes with a rich collection of pre-defined placement patterns. If you find a placement pattern you like you can simply use it as is and the symbolic editor will generate a correct by construction placement that you can instantiate in you layout. If you don’t find an exact match you can easily use a pattern that is similar to what you need and rearrange the placement pattern graphically. No constraints to enter, no code to write and layout is done in minutes versus hours.


Example of patterns for a differential pair

Through the symbolic editor the layout engineer can make simple graphical choices of how the layout needs to look and then have the placement taken care of by the placement engine. You can easily add or remove placement rows and columns as well as insert dummy devices. The symbolic editor also supports device merging and splitting and is the fastest way to achieving correct layout. The symbolic editor is particularly well suited for FinFET based designs and is equally as good on planar CMOS nodes. Generating the devices and placing them such that they meet all the design rules and will produce a robust working design is about 30% of the layout time. Using a layout assistant like the symbolic editor really speeds this task up and allows the layout engineer to gain back some of the productivity that gets lost due to the complexity of the FinFET process.

Check out this video link to see the symbolic editor in action.

Register here for a webinar on Custom Compiler.

Next we will take a look at another layout assistant, but that’s another post.