Custom Layout Insights: Analog/Custom Layout Blog

 

The wait is over!

The wait is over!

Remember the last few blogs where I was outlining the kind of tools you really need to tackle FinFET? Well they are here right now, because today Synopsys unveiled Custom Compiler and ushered in a new era of Visually-assisted Automation. Check out this link: http://www.customcompiler.info

It’s all the good stuff I was alluding to in prior posts, a new custom design solution that closes the FinFET productivity gap by shortening custom design tasks from days to hours.

This is not a revamp of the old constraint-based legacy approach, it’s a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse. What’s Visually-assisted Automation you may ask?

Well, Visually-assisted Automation is the collective term we use for a set of productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. The job of the assistants is to deal with routine and repetitive tasks automatically without extra setup. Custom Compiler provides four types of assistants: Layout, In-Design, Template and Co-Design. For now here’s quick outline of each assistant. I will talk about these in more detail in my next series of posts.

Layout Assistants speed layout with visually-guided automation of custom device placement and routing. The router is ideal for connecting FinFET arrays or large-M factor transistors. It automatically clones connections and creates pin taps. The user simply guides the router with the mouse and it fills in the details automatically. The placer uses a new innovative approach to device placement. It allows the user to make successive refinements, offering placement choices but leaving the layout designer in full control of the results—without requiring any up-front textual constraint entry.

In-Design Assistants reduce costly design iterations by catching physical and electrical errors before signoff verification. Custom Compiler includes a built-in design rule checking (DRC) engine, which is extremely fast and can be active all the time. In addition to the DRC engine, electromigration checking, and resistance and capacitance extraction are all natively implemented in Custom Compiler. Unlike other “electrically-aware” tools, Custom Compiler’s extraction is based on Synopsys’ gold-standard StarRC™ engine.

Template Assistants help designers reuse existing know-how by making it easy to apply previous layout decisions to new designs. Template Assistants actually learn from the work done with the Layout Assistant’s custom device placer and router. They intelligently recognize circuits that are similar to ones that were already completed and enable users to apply the same placement and routing pattern as a template to the new circuits. Custom Compiler comes pre-loaded with a set of built-in templates for commonly used circuits, such as current mirrors, level shifters and differential pairs.

Co-Design Assistants combine IC Compiler™ and Custom Compiler into a unified solution for custom and digital implementation. Users can freely move back and forth between Custom Compiler and IC Compiler, using the commands of each to successively refine their designs.  With the Co-Design Assistants, IC Compiler users can perform full custom edits to their digital designs at any stage of implementation. Likewise, Custom Compiler users can use IC Compiler to implement digital blocks in their custom designs. The lossless, multi-roundtrip capability of the Co-Design Assistants ensures that all changes are synchronized across both the digital and custom databases.

This is really exciting stuff and you can see it in action today at the Silicon Valley SNUG. So get yourselves along there and hear from customers and our R&D teams about Custom Compiler.

Oh and don’t forget to check back here for more details.

Graham