What do layout engineers really need for FinFET – part 2.

In the last of blog we outlined the kind of tool that the layout engineer needs in order to get a good placement that delivers robust working silicon within the confines of the FinFET process. We concluded that a guided / interactive approach that is fast and easy to refine such that you do get the result you want is the way to go.

So where else can we look for more efficiency during layout? Well once you have placed your devices the next step is to route up all the connections that cannot be completed by simple abutment. Again, because you could be dealing with hundreds of devices (remember the differential pair example? Click here to link to the article) the routing task is one that absolutely screams out for an automatic approach and there have been lots of efforts at automating custom routing in the past.

The downside with past custom routing solutions is that they require you to enter a lot of text-based constraints to get anything near to what you really want. Sure you need some level of constraints to tell the router which layers are valid and which direction they can route in. And of course, you do need to tell the router what the DRC rules are. But, you should not have to spend precious layout time teaching a router what to do for your particular layout topology only to find it does not give you exactly what you want and you have to go edit the results anyway.

So where does that leave us? Well I firmly believe that the guided / interactive approach is the best way to quickly converge on the routing style you need. But we could have hundreds of devices you may say. Are we going to have to do all the connections one by one?  Well, if you have the right kind of router the answer is no, you won’t have to do them one by one.

What’s required is the kind of router that allows you to simply click on the starting point for the route and drag the cursor in the direction you want the route to go.  An ideal router would automatically handle the connections to the array of FinFETs including any common routing and the end result would also adhere to the correct coloring rules and metal grids. This approach would not be just pretty cool; it would also give the layout engineer control of what the route looks like and would take the tedium out of having to do the connections one by one. Because the feedback would be visual (you would see the routing appearing and in real time) the layout engineer would be able to make informed decisions as to whether to keep the current routing topology or change it to a different style.

This powerful combination of user guidance and automatic routing would be another surefire way to reclaim custom layout productivity. And there is more.

But that’s another post.

Graham