Custom Layout Insights: Analog/Custom Layout Blog


Current solutions for FinFET – part 3.

What is Electro-migration and why is it something we should care about?

Here’s the definition of Electro-migration from Wikipedia: “Electro-migration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms.”

Put simply, when the current density gets too high for a given wire width, you get problems. These problems manifest themselves in two ways, either a void in the metal wire that creates an open circuit or a hillock that creates a short to another wire. Either way your chip fails. Electro-migration is made worse by temperature and mechanical stresses.


Electro-migration in the FinFET process is now a first order effect and has a huge impact on the Mean Time To Failure (MTTF) of a metal wire. So as you can imagine to ensure you have a robust design that will last, great care has to be taken when choosing wire widths for interconnect and power grids.

So what tools do we have to help us in determining the correct wire widths for our interconnect?

There are a variety of tools that will help you check on EM compliance. They range from full blown ‘sign off’ tools to fast static checkers that can be run whilst doing the custom physical layout.

For sign off, Synopsys’s CustomSim can calculate current densities in narrow signal nets to determine their susceptibility to EM. Bidirectional current flow is correctly considered, including calculation of the RMS currents required for monitoring Joule heating within the design. CustomSim can also include all of the design’s extracted coupling capacitors in addition to the grounded capacitors. This provides a high level of precision in determining the current entering or leaving segments of signal net interconnect, enhancing the quality of results. The results are presented as GDSII files which can be overlaid on the design for visualization of the errors.

For the layout engineer, having the ability to run a fast static check interactively during layout is an easy way to catch errors up front. To run EM checks you need to set up the design with the sheet resistance models for the individual layers. The data for these models comes from the Interconnect Technology File (ITF) that is delivered as part of the iPDK. Once that data is processed you then set up the current density constraints and the current values on the ports and pins of blocks and devices. The current values can be average, peak and RMS. Now with this information at hand any net you route to these pins can be checked for EM compliance. To run an EM check you simply select the routed net of interest and invoke the checker. Any EM errors are flagged in the layout with a blinking error marker and an error browser gives detailed information on the type of error and how to fix it.


This is a fast and easy way to ensure EM compliance whilst implementing the layout.

So there we have it. Yes FinFET is complex and there are lots of rules and regulations that you have to abide by to ensure a robust and functioning design. But help is at hand and as we have discussed in these last few posts, the layout engineer can call on a good number of tools to help automate the physical layout process.

So the next question is do we need more automation? What do the layout engineers really want?

Well that’s another post.