Custom Layout Insights: Analog/Custom Layout Blog


Hurricane FinFET – part 3

So, what do you have to do for routing? Well again, drawing on the experience of my layout colleagues who are still ‘in the business’ and dealing with FinFETs, here are a few landmines you will have to deal with.

One particular issue they encounter is the fact that although the base layers have shrunk considerably, the shrink of the routing layers has not kept pace. Each new node has brought us smaller transistors but the minimum metal pitch has not really changed. This really impacts layout floor planning because designs that were once dictated by device area are now dictated by the ability to route the required signals. Double / triple patterning compounds the issue even further.

Planning which metal shape goes on which color (mask) is key, especially when propagating connections through the layout hierarchy. Highly matched signals such as complementary clocks must be assigned to the same color, as routes on different masks have different resistances. In addition designers now need to be aware of spacing rules for opposite-mask routes and same-mask routes whilst still meeting color density rules. And there’s more.

Strict rules for metal direction may also include a restriction on the ability to add a notch or a turn into the route. Couple that with limited metal width and via combinations and you have to rethink how you make a strong well connected route that meets reliability criteria. Topologies that were ok on planar nodes like in Figure 1 may now have to be redesigned as in Figure 2.

            routing_1                                                        routing_2

Figure 1 – multiple vias in a planar process.                                  Figure 2 – multiple vias in a FinFET process

And then there is the little matter of electro migration (EM). Because the resistivity of the lower level metals is much higher in a FinFET process, you have to be acutely aware of EM and IR drop. Care must be taken when planning which metals to use and in fact track planning becomes essential for a design to pass EM and IR checks.

So there we have it. Designing with a FinFET process is like a game of snakes and ladders. You need to roll the dice carefully and avoid the snakes whilst climbing the ladders to FinFET heaven.

So what tools and techniques do today’s designers have at their disposal to deal with FinFET?

Well there are quite a few.

But that’s another post.